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P4: A platform for FPGA implementation of protocol boosters

  • Ilija Hadžić
  • Jonathan M. Smith
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1304)

Abstract

Protocol Boosters are functional elements, inserted and deleted from network protocol stacks on an as-needed basis. The Protocol Booster design methodology attempts to improve end-to-end networking performance by adapting protocols to network dynamics.

We describe a new dynamically reconfigurable FPGA based architecture, called the Programmable Protocol Processing Pipeline (P4), which provides a platform for highly-flexible hardware implementations of Protocol Boosters. The prototype P4 is designed to interface to an OC3 (155 Mb/s) ATM link and perform selected boosting functions at this line rate.

The FPGA devices process the data stream as a pipeline of processing elements. Processing elements are downloaded and activated dynamically, based on policies used by the controller to choose configurations. As modules become unnecessary they are removed from the pipeline chain.

Keywords

Processing Element Asynchronous Transfer Mode Virtual Channel FPGA Device Asynchronous Transfer Mode Network 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • Ilija Hadžić
    • 1
  • Jonathan M. Smith
    • 1
  1. 1.Distributed Systems LaboratoryUniversity of PennsylvaniaPennsylvania

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