A high-speed scalable CMOS current-mode Winner-Take-All network
A CMOS modular high-speed current-mode 2-input Winner-Take-All (2-WTA) circuit for use in VLSI tree-structure WTA networks is described. The classification speed of the design is not input pattern dependent, but is a function of the value of the largest current input only. Simulations show that the new circuit can resolve input currents differing by less than 1μA with a negligible loss of operating speed. Detailed simulations and preliminary measured results of a single WTA cell and of a complete 8-input tree WTA network are presented.
KeywordsInput Current Forward Pass Classification Speed HSPICE Simulation Logic Circuitry
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