A high-speed scalable CMOS current-mode Winner-Take-All network

  • Andreas Demosthenous
  • John Taylor
  • Sean Smedley
Oral Presentations: Implementations Implementations: Dynamic and Massively Parallel Networks
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1112)


A CMOS modular high-speed current-mode 2-input Winner-Take-All (2-WTA) circuit for use in VLSI tree-structure WTA networks is described. The classification speed of the design is not input pattern dependent, but is a function of the value of the largest current input only. Simulations show that the new circuit can resolve input currents differing by less than 1μA with a negligible loss of operating speed. Detailed simulations and preliminary measured results of a single WTA cell and of a complete 8-input tree WTA network are presented.


Input Current Forward Pass Classification Speed HSPICE Simulation Logic Circuitry 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    R. Lippmann, “An introduction to computing with neural nets,” IEEE ASSP Mag., vol. 4, pp. 4–22, Apr 1987.Google Scholar
  2. 2.
    J. Ramirez-Angulo, “Building blocks for fuzzy processors,” IEEE Circuits & Devices Mag., vol. 10, pp. 48–50, Jul. 1994.Google Scholar
  3. 3.
    D. Grant, J. Taylor, and P. Houselander, “Design, implementation and evaluation of a high-speed integrated Hamming neural classifier,” IEEE J. Solid-State Circuits”, vol. 29, pp. 1154–1157, Sep. 1994.Google Scholar
  4. 4.
    J. Choi and B. Sheu, “A high-precision VLSI winner-take-all circuit for self-organising neural networks,” IEEE J. Solid-State Circuits, vol. 28, pp. 576–584, May 1993.Google Scholar
  5. 5.
    U. Cilingiroglu, “A charge-based neural Hamming classifier,” IEEE J. Solid-State Circuits, vol. 28, pp. 59–67, Jan. 1993.Google Scholar
  6. 6.
    S. Smedley, J. Taylor, and M. Wilby, “A scalable high-speed current-mode winner-take-all network for VLSI neural applications,” IEEE Trans. Circuits and Systems-Part I, vol. 42, pp. 289–291, May 1995.Google Scholar
  7. 7.
    K. Laker and W. Sansen, Design of Analog Integrated Circuits and Systems. USA: McGraw-Hill, 1994, pp. 385–386.Google Scholar
  8. 8.
    G. Di Cataldo, G. Palumbo and S. Stivala, “New CMOS current mirrors with improved high-frequency response,” Int. J. Circuit Theory and Applications, pp. 443–450, 1993.Google Scholar
  9. 9.
    C. Das, “MIETEC 2.4 μm CMOS MPC — Electrical parameters,” EUROCHIP Service Org. (RAL), Didcot, UK, Doc. MIE/F/02, Jan. 1993.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • Andreas Demosthenous
    • 1
  • John Taylor
    • 1
  • Sean Smedley
    • 2
  1. 1.Department of Electronic and Electrical EngineeringUniversity CollegeLondonUK
  2. 2.Data Conversion SystemsDirac HouseCambridgeUK

Personalised recommendations