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A high-speed scalable CMOS current-mode Winner-Take-All network

  • Andreas Demosthenous
  • John Taylor
  • Sean Smedley
Oral Presentations: Implementations Implementations: Dynamic and Massively Parallel Networks
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1112)

Abstract

A CMOS modular high-speed current-mode 2-input Winner-Take-All (2-WTA) circuit for use in VLSI tree-structure WTA networks is described. The classification speed of the design is not input pattern dependent, but is a function of the value of the largest current input only. Simulations show that the new circuit can resolve input currents differing by less than 1μA with a negligible loss of operating speed. Detailed simulations and preliminary measured results of a single WTA cell and of a complete 8-input tree WTA network are presented.

Keywords

Input Current Forward Pass Classification Speed HSPICE Simulation Logic Circuitry 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • Andreas Demosthenous
    • 1
  • John Taylor
    • 1
  • Sean Smedley
    • 2
  1. 1.Department of Electronic and Electrical EngineeringUniversity CollegeLondonUK
  2. 2.Data Conversion SystemsDirac HouseCambridgeUK

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