An analog CMOS neural network with on-chip learning and multilevel weight storage

  • M. Conti
  • G. Guaitini
  • C. Turchetti
Poster Presentations 2 Implementations
First Online:
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1112)

Abstract

An analog neural network with four neurons and 16 synapses, fabricated in a 1.2 μm n-well single-polysilicon, double-metal process, is presented. The circuit solutions adopted, for on-chip learning and weight storage, particularly simple and silicon area-efficient, are capable of solving the main problems to the implementation of analog neural networks.

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References

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Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • M. Conti
    • 1
  • G. Guaitini
    • 1
  • C. Turchetti
    • 1
  1. 1.Dept. of ElectronicsUniv. of AnconaAnconaItaly

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