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Symbolic model checking

  • E. Clarke
  • K. McMillan
  • S. Campos
  • V. Hartonas-Garmhausen
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1102)

Abstract

Symbolic model checking is a powerful formal specification and verification method that has been applied successfully in several industrial designs. Using symbolic model checking techniques it is possible to verify industrial-size finite state systems. State spaces with up to 1030 states can be exhaustively searched in minutes. Models with more than 10120 states have been verified using special techniques.

Several extensions to the original technique have been developed, making it even more powerful. Timing properties can be verified by performing a quantitative timing analysis [3, 5]. The designer can then analyze the performance of a system and gain insight in how well a system works early in the design process. Word-level model checking allows the verification of datapaths in addition to control [12]. Symmetry [8], abstraction [10, 15] and compositional reasoning [15] techniques significantly extend the power of model checking by exploiting the hierarchical structure of complex circuit designs and protocols.

More information about SMV, as well as the source code for the model checker can be found at: http://www.cs.cmu.edu/∼modelcheck

Keywords

Model Check Temporal Logic Binary Decision Diagram Computation Tree Logic Symbolic Model Check 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • E. Clarke
    • 1
  • K. McMillan
    • 2
  • S. Campos
    • 1
  • V. Hartonas-Garmhausen
    • 1
  1. 1.School of Computer ScienceCarnegie Mellon UniversityPittsburghUSA
  2. 2.Cadence LabsBerkeleyUSA

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