Symbolic model checking

  • E. Clarke
  • K. McMillan
  • S. Campos
  • V. Hartonas-Garmhausen
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1102)


Symbolic model checking is a powerful formal specification and verification method that has been applied successfully in several industrial designs. Using symbolic model checking techniques it is possible to verify industrial-size finite state systems. State spaces with up to 1030 states can be exhaustively searched in minutes. Models with more than 10120 states have been verified using special techniques.

Several extensions to the original technique have been developed, making it even more powerful. Timing properties can be verified by performing a quantitative timing analysis [3, 5]. The designer can then analyze the performance of a system and gain insight in how well a system works early in the design process. Word-level model checking allows the verification of datapaths in addition to control [12]. Symmetry [8], abstraction [10, 15] and compositional reasoning [15] techniques significantly extend the power of model checking by exploiting the hierarchical structure of complex circuit designs and protocols.

More information about SMV, as well as the source code for the model checker can be found at:∼modelcheck


Model Check Temporal Logic Binary Decision Diagram Computation Tree Logic Symbolic Model Check 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, C-35(8), 1986.Google Scholar
  2. 2.
    J. R. Burch, E. M. Clarke, K. L. McMillan, D. L. Dill, and J. Hwang. Symbolic model checking: 1020 states and beyond. In Symposium on Logic in Computer Science, 1990.Google Scholar
  3. 3.
    S. Campos, E. Clarke, W. Marrero, and M. Minea. Verifying the performance of the PCI local bus using symbolic techniques. In International Conference on Computer Design, 1995.Google Scholar
  4. 4.
    S. V. Campos, E. M. Clarke, W. Marrero, and M. Minea. Timing analysis of industrial realtime systems. In Workshop on Industrial-strength Formal specification Techniques, 1995.Google Scholar
  5. 5.
    S. V. Campos, E. M. Clarke, W. Marrero, M. Minea, and H. Hiraishi. Computing quantitative characteristics of finite-state real-time systems. In IEEE Real-Time Systems Symposium, 1994.Google Scholar
  6. 6.
    E. M. Clarke and E. A. Emerson. Synthesis of synchronization skeletons for branching time temporal logic. In Logic of Programs: Workshop, Yorktown Heights, NY, May 1981. Springer-Verlag, 1981, Lecture Notes in Computer Science, volume 131.Google Scholar
  7. 7.
    E. M. Clarke, E. A. Emerson, and A. P. Sistla. Automatic verification of finite-state concurrent systems using temporal logic specifications. ACM Transactions on Programming Languages and Systems, 8(2):244–263, 1986.CrossRefGoogle Scholar
  8. 8.
    E. M. Clarke, T. Filkorn, and S. Jha. Exploiting symmetry in temporal logic model checking. In Proceedings of the Fifth Workshop on Computer-Aided Verification, June 1994.Google Scholar
  9. 9.
    E. M. Clarke, O. Grumberg, H. Hiraishi, S. Jha, D. E. Long, K. L. McMillan, and L. A. Ness. Verification of the Futurebus+cache coherence protocol. In L. Claesen, editor, International Symposium on Computer Hardware Description Languages and their Applications. North-Holland, April 1993.Google Scholar
  10. 10.
    E. M. Clarke, O. Grumberg, and D. E. Long. Model checking and abstraction. In Proceedings of the Nineteenth Annual ACM Symposium on Principles of Programming Languages, January 1992.Google Scholar
  11. 11.
    E. M. Clarke, O. Grumberg, and D. E. Long. Verification tools for finite-state concurrent systems. In A Decade of Concurrency — Reflections and Perspectives, 1994. Springer Lecture Notes in Computer Science, 803.Google Scholar
  12. 12.
    E. M. Clarke, M. Khaira, and X. Zhao. Word level model checking — avoiding the pentium FDIV error. In Design Automation Conference, June 1996.Google Scholar
  13. 13.
    V. Hartonas-Garmhausen, E.M. Clarke, and S. Campos. Deadlock prevention in flexible manufacturing systems using symbolic model checking. In International Conference on Robotics and Automation, 1996.Google Scholar
  14. 14.
    V. Hartonas-Garmhausen, T. Kurfess, E.M. Clarke, and D. Long. Automatic verification of industrial designs. In Workshop on Industrial-strength Formal specification Techniques, 1995.Google Scholar
  15. 15.
    D. E. Long. Model checking, abstraction and compositional reasoning. PhD thesis, SCS, Carnegie Mellon University, 1993.Google Scholar
  16. 16.
    K. L. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, 1993.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • E. Clarke
    • 1
  • K. McMillan
    • 2
  • S. Campos
    • 1
  • V. Hartonas-Garmhausen
    • 1
  1. 1.School of Computer ScienceCarnegie Mellon UniversityPittsburghUSA
  2. 2.Cadence LabsBerkeleyUSA

Personalised recommendations