Symbolic Timing Diagrams
We present a novel method for controller synthesis and verification from high-level interface specifications. Specifications are expressed in the form of requirements using Symbolic Timing Diagrams, which is a visual formalism based on the notion of timing diagrams commonly used by hardware designers.
We suggest a top-down design methodology where specifications are created incrementally and discuss two different specification styles found while we applied the method to synthesize a distributed controller for the production cell.
We then introduce the ICOS2 system, which has been used to carry out the practical work. ICOS2 allows to analyze specifications for consistency and completeness and to synthesize C- and VHDL-code from the given specifications automatically.
KeywordsOutput Port Controller Module Timing Diagram Synthesis Step Symbolic Timing
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