Advertisement

Statecharts

Using graphical specification languages and symbolic model checking in the verification of a production cell
  • Werner Damm
  • Hardi Hungar
  • Peter Kelb
  • Rainer Schlör
Chapter
Part of the Lecture Notes in Computer Science book series (LNCS, volume 891)

Abstract

This paper discusses specification and verification of the production cell using symbolic model checking. Key features of the presented approach are the clean separation between (models of the) components of the production cell and the controller itself, the use of graphical specification techniques, and the application of methods and tools allowing compositional automatic design verification.

Keywords

Model Check Production Cell Temporal Logic Timing Diagram Liveness Property 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    E.M. Clarke, E.A. Emerson and A.P. Sistla. Automatic Verification of Finite State Concurrent Systems Using Temporal Logic Specifications: A Practical Approach. In Proceedings of the 10th ACM Symposium on Principles of Programming Languages, 1983, pp. 117–126.Google Scholar
  2. [2]
    D. Harel. Statecharts: A Visual Formalism for Complex Systems. Science of Computer Programming, vol. 8, 1987, pp. 231–274.Google Scholar
  3. [3]
    Z. Manna and A. Pnueli. Models for reactivity. Acta Informatica, 1993, to appear.Google Scholar
  4. [4]
    J. R. Burch, E.M. Clarke, K.L. McMillan, D.L. Dill and J. Hwang. Symbolic Model Checking: 1020 States and Beyond. In Proceedings of the Fifth Annual Conference on Logic in Computer Science, Jun 1990, pp. 428–439.Google Scholar
  5. [5]
    Z. Manna and A. Pnueli. Verifying Hybrid Systems. In Proc. Workshop on Hybrid Systems, LNCS, Springer Verlag, 1993.Google Scholar
  6. [6]
    Werner Damm, Bernhard Josko and Rainer Schlör. System-Level Verification of VHDL-based Hardware Designs. In Specification and Validation Methods for Programming Languages and Systems. Oxford University Press, 1993, to appear.Google Scholar
  7. [7]
    Rainer Schlör and Werner Damm. Specification and verification of system-level hardware designs using timing diagrams. In The European Conference on Design Automation with the European Event in ASIC Design, 1993, pp. 518–524.Google Scholar
  8. [8]
    Th. Lindner. Case Study Production Cell: Task Definition. Forschungszentrum Informatik, Haid-und-Neu-Strasse 10–14, 76131 Karlsruhe, Germany, 1993.Google Scholar
  9. [9]
    M. Hansen and E.-R. Olderog. Constructing Circuits from Decidable Duration Calculus. Technical report, University of Oldenburg, 26111 Oldenburg, Germany, 1993.Google Scholar
  10. [10]
    J. Helbig, R. Schlör, W. Damm, G. Doehmen and P. Kelb. VHDL/S — integrating Statecharts, timing diagrams, and VHDL. Microprocessing and Microprogramming 38, 1993, pp. 571–580.Google Scholar
  11. [11]
    J. Helbig and P. Kelb. An OBDD-Representation of Statecharts. EDAC, 1994, to appear.Google Scholar
  12. [12]
    R.E. Bryant. Graph-based algorithms for boolean function manipulation. In IEEE Transactions on Computer, C-35(8), 1986.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1995

Authors and Affiliations

  • Werner Damm
    • 1
  • Hardi Hungar
    • 1
  • Peter Kelb
    • 1
  • Rainer Schlör
    • 1
  1. 1.Universität Oldenburg and OFFIS OldenburgGermany

Personalised recommendations