Genetic algorithm based design optimization of CMOS VLSI circuits

  • Anthony M. Hill
  • Sung-Mo (Steve) Kang
Applications
Part of the Lecture Notes in Computer Science book series (LNCS, volume 866)

Abstract

The proliferation of portable and hand-held electronics combined with increasing packaging costs is forcing circuit designers to adopt low power design methodologies. Low power designs of microprocessors and application specific integrated circuits (ASICs) result in increased battery life and improved reliability. In this paper, we examine the application of genetic algorithms to the low-power design of combinational logic. In particular, we consider the use of genetic algorithms for the optimization of standard cell based designs which account for 20–50% of a typical microprocessor die size. Our algorithm optimizes a user-specified function of delay, power, and area under performance constraints. Empirically, we find that the run time for our algorithm scales linearly with circuit size. In our extensive benchmark suite, this algorithm has reduced power by 17% on the average and as much as 24% on some circuits.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Geppert, L. The new contenders. IEEE Spectrum (December 1993) 20–25Google Scholar
  2. 2.
    Bell, T. Incredible shrinking computers. IEEE Spectrum (May 1991) 37–43Google Scholar
  3. 3.
    Eager. Advances in rechargeable batteries pace portable computer growth. Proceedings Silicon Valley Personal Computer Conference (1991) 693–697Google Scholar
  4. 4.
    Bakoglu, H. B. Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley (1990)Google Scholar
  5. 5.
    Chan, P. Algorithms for library-specific sizing of combinational logic. Proceedings of the 27th ACM/IEEE Design Automation Conference (1990) 353–356Google Scholar
  6. 6.
    Lin, S., Marek-Sadowska, M., Kuh, E. Delay and area optimization in standardcell design. Proceedings of the 27th ACM/IEEE Design Automation Conference (1990) 349–352Google Scholar
  7. 7.
    Li, W., Lim, A., Agrawal, P., Sahni, S. On the circuit implementation problem. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. 12(8) (1993) 1147–1156CrossRefGoogle Scholar
  8. 8.
    Li, W., Lim, A., Agrawal, P., Sahni, S. On the circuit implementation problem. Proceedings of the 29th. ACM/IEEE Design Automation Conference (1993) 478–483Google Scholar
  9. 9.
    Singh, K., Sangiovanni-Vincentelli, A. A heuristic algorithm for the fanout problem. Proceedings of the 27th ACM/IEEE Design Automation Conference (1990) 357–360Google Scholar
  10. 10.
    Ghosh, A., Devadas, S., Keutzer, K., White, J. Estimation of average switching activity in combinational and sequential circuits. Proceedings of the 29th ACM/IEEE Design Automation Conference (1992) 253–259Google Scholar
  11. 11.
    Sentovich, E. et al. Sequential circuit design using synthesis and optimization. Proceedings of the International Conference on Computer Design (1992) 328–333Google Scholar

Copyright information

© Springer-Verlag 1994

Authors and Affiliations

  • Anthony M. Hill
    • 1
  • Sung-Mo (Steve) Kang
    • 1
  1. 1.Department of Electrical and Computer Engineering and Coordinated Science LaboratoryUniversity of Illinois at Urbana-ChampaignUrbana

Personalised recommendations