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Implementing on line arithmetic on PAM

  • Marc Daumas
  • Jean-Michel Muller
  • Jean Vuillemin
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 849)

Abstract

On line arithmetic is a computation tool able to adapt to the precision expected by the user. Developing a library of on line operators for FPGAs will lead in a near future to the spread of brick-assembled application-dedicated operators. In the implementation of the basic arithmetic operations (addition, multiplication, division and square root), we have met some new problems: our work has involved changes in the VLSI design methodology in order to achieve some effective performances. We shall present the modified on-line algorithms and their adaptation to the cell oriented FPGA architecture. The correct integration of some retiming barriers has proved to be critical as far as speed is concerned.

Keywords

Clock Cycle Logic Cell Correct Integration Reset Signal Root Operation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    A. Avizienis, “Signed digit number representation for fast parallel arithmetic”, IRE Transaction on Electronic Computers, Volume EC-10, 1961.Google Scholar
  2. 2.
    J.C. Bajard, J. Duprat, S. Kla & J.M. Muller, “Some operators for on-line radix 2 computation”, to appear in Journal of Parallel and Distributed Computing, also available from Laboratoire de l'Informatique du Parallélisme RR 92-42, October 1992.Google Scholar
  3. 3.
    P. Bertin, D. Roncin & J. Vuillemin, “Introduction to programmable active memories,” Systolic Array Processors, Prentice Hall, also available from Paris Research Laboratory, PRL-RR 24, March 1993.Google Scholar
  4. 4.
    C.Y. Chow & J.E. Robertson, “Logical design of a redundant binary adder”, 4th IEEE Symposium on Computer Arithmetic, October 1978.Google Scholar
  5. 5.
    M.D. Ercegovac, “On line arithmetic: an overview”, Real Time Signal Processing VII, SPIE, Volume 495.Google Scholar
  6. 6.
    -, “A general hardware oriented method for evaluation of functions and computations in a digital computer”, IEEE Transactions on Computers, Volume C-26, N. 7, July 1977.Google Scholar
  7. 7.
    S. Kla Koué, “Calcul parallèle et en ligne des fonctions arithmétiques,” Laboratoire de l'Informatique du Parallélisme, PhD Dissertation 31–93, February 1993.Google Scholar
  8. 8.
    M.E. Louie & M.D. Ercegovac, “On digit recurrence division implementations for field programmable gate arrays”, 11th IEEE Symposium on Computer Arithmetic, June 1993.Google Scholar
  9. 9.
    J.M. Muller, “Some characterization of functions computable in on-line arithmetic,” to appear in IEEE Transactions on Computers, also available from Laboratoire de l'Informatique du Parallélisme RR 91-15, 1991.Google Scholar
  10. 10.
    K.S. Trivedi & M.D. Ercegovac, “On line algorithm for division and multiplication,” IEEE Transactions on Computers, Volume C-26 (7), July 1977.Google Scholar
  11. 11.
    Xilinx Inc., “The programmable gate array data book,” Product Briefs, Xilinx, 1987.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Marc Daumas
    • 1
  • Jean-Michel Muller
    • 1
  • Jean Vuillemin
    • 2
  1. 1.Laboratoire de l'Informatique du Parallélisme-CNRSÉcole Normale Supérieure de LyonLyonFrance
  2. 2.Paris Research LaboratoryDigital Equipment Corporation Rueil MalmaisonFrance

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