Formal verification of timing rules in design specifications

  • Tibor Bartos
  • Norbert Fristacky
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 849)


An algorithm for formal verification of the set of timing rules that express timing discipline in digital systems is described. It is based on a digital system specification model and notation transferrable to VHDL and concerns formal consistency verification at the design level of system specification development procedure.


Timing Event Finite State Machine Digital System Timing Diagram Formal Verification 
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  1. [1]
    Fristacky, N., Cingel, V.: A functional and timing specification model for digital systems. Proc. of the 7th Symp. on Microcomp. and Microproc. App., Budapest, 1992, pp. 185–190.Google Scholar
  2. [2]
    Cingel, V.: A graph based method for timing diagrams representation and verification. In Correct Hardware Design Methodol. CHARME 93, Arles France, Springer Verlag, 1993.Google Scholar
  3. [3]
    Cingel, V.: Specification and Verification of Timing in Digital Systems. Ph.D. Thesis, Dept. of Comp. Science and Eng., Slovak Techn. Univ., Bratislava, 1991 (in Slovak).Google Scholar
  4. [4]
    Bartos, T.: Program for Verification of Timing Rules in Digital System Specifications. Diploma Thesis, Faculty of El. Eng., Slovak Techn. Univ., Bratislava, 1993 (in Slovak).Google Scholar
  5. [5]
    Jahanian, F., Mok, A. K.: A Graph-theoretic Approach for Timing Analysis and its Implementation. IEEE Tr. on Computer, Vol. 8, 1987, pp. 961–975.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Tibor Bartos
  • Norbert Fristacky

There are no affiliations available

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