FPL 1994: Field-Programmable Logic Architectures, Synthesis and Applications pp 11-22 | Cite as
A test methodology applied to Cellular logic Programmable Gate Arrays
Abstract
This paper describes an approach for testing a class of programmable logic devices called Cellular Programmable Gate Arrays. The flexibility in the selection of logic functions and the high number of interconnections in this class of devices turns test a complex task. It has led to the proposition of an efficient test procedure based on some function properties. The regularity of the procedure permits that all logic cells in the device can be tested completly for functional faults at the same time, whenever is possible. It provides a reduced number of reprogramming times during test mode and a possibility of testing more devices in a defined period of time.
Keywords
Greedy Algorithm Field Programmable Gate Array Sequential Function Functional Fault Programmable DevicePreview
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