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Fault modeling and test generation for FPGAs

  • Michael Hermann
  • Wolfgang Hoffmann
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 849)

Abstract

This paper derives a fault model for one-time programmable FPGAs from the general functional fault model and an algorithm to perform test generation according to this model. The new model is characterized by the abstraction of functional faults from a set of possible implementations of a circuit. In contrast to other functional-level test generation procedures a fault coverage of 100% can be achieved regardless of the final implementation of the circuit.

Keywords

Boolean Function Logic Module Test Generation Field Programmable Gate Array Function Identification 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Michael Hermann
    • 1
  • Wolfgang Hoffmann
    • 1
  1. 1.Institute of Electronic Design Automation, Department of Electrical EngineeringTechnical University of MunichMunichGermany

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