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Datarol-II: A fine-grain massively parallel architecture

  • Tetsuo Kawano
  • Shigeru Kusakabe
  • Rin-ichiro Taniguchi
  • Makoto Amamiya
Poster Session
Part of the Lecture Notes in Computer Science book series (LNCS, volume 817)

Abstract

In this paper, we introduce the Datarol-II processor, that can efficiently execute a fine-grain multi-thread program, called Datarol. In order to achieve the efficient multi-thread execution by reducing context switching overhead, we introduce an implicit register load/store mechanism in the execution pipeline. A two-level hierarchical memory system is also introduced in order to reduce memory access latency. The simulation results show that the Datarol-II processor can tolerate remote memory access latencies and execute a fine-grain multi-thread program efficiently.

Keywords

Memory Access Physical Register Utilization Ratio Context Switching Register Buffer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    M.Amamiya and R.Taniguchi, “Datarol: A Massively Parallel Architecture for Functional Language”, Proc. SPDP, pp.726–735, (1990)Google Scholar
  2. 2.
    S.Kusakabe, T.Hoshide, R.Taniguchi and M.Amamiya, “Parallelism Control and Storage Management in Datarol PE”, Proc. IFIP World Congress, Vol.1, pp.535–541, (1992)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Tetsuo Kawano
    • 1
  • Shigeru Kusakabe
    • 1
  • Rin-ichiro Taniguchi
    • 1
  • Makoto Amamiya
    • 1
  1. 1.Department of Information Systems, Graduate School of Engineering SciencesKyushu UniversityJapan

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