Verification of timing properties of VHDL

  • Costas Courcoubetis
  • Werner Damm
  • Bernhard Josko
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 697)


This paper shows how timing properties of VHDL processes can be verified using timed transition systems. The timing model being adopted is the timed automaton model used in the timing extension of Kurshan's COSPAN system. It demonstrates how a VHDL process can be translated into a timed automaton by describing the construction of the corresponding timed process that handles the scheduled signal assignments of the VHDL specification. Verification is performed in the case in which the complement of the timing properties to be verified are provided in terms of a timed automaton. Interestingly enough, this is the case for a large class of hardware properties expressed in terms of timing diagrams.


Timing Diagram Signal Assignment Event Graph Wait Statement Control Graph 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • Costas Courcoubetis
    • 1
    • 2
  • Werner Damm
    • 3
  • Bernhard Josko
    • 3
  1. 1.Department of Computer ScienceUniversity of CreteGreek
  2. 2.Institute of Computer ScienceForthGreek
  3. 3.Department of Computer ScienceUniversity of OldenburgGermany

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