Advertisement

Verification of timing properties of VHDL

  • Costas Courcoubetis
  • Werner Damm
  • Bernhard Josko
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 697)

Abstract

This paper shows how timing properties of VHDL processes can be verified using timed transition systems. The timing model being adopted is the timed automaton model used in the timing extension of Kurshan's COSPAN system. It demonstrates how a VHDL process can be translated into a timed automaton by describing the construction of the corresponding timed process that handles the scheduled signal assignments of the VHDL specification. Verification is performed in the case in which the complement of the timing properties to be verified are provided in terms of a timed automaton. Interestingly enough, this is the case for a large class of hardware properties expressed in terms of timing diagrams.

Keywords

Timing Diagram Signal Assignment Event Graph Wait Statement Control Graph 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    R. Alur, C. Courcoubetis, and D. Dill. Model-checking for real-time systems. In Proceedings of the 5th Symp. on Logic in Computer Science, pp. 414–425, 1990.Google Scholar
  2. 2.
    R. Alur, C. Courcoubetis, N. Halbwachs, D. Dill, and H. Wong-Toi. Minimization of timed transition systems. In CONCUR 92: Theories of Concurrency, LNCS 630, pp. 340–354, 1992.Google Scholar
  3. 3.
    R. Alur and D. Dill. Automata for modelling real-time systems. In ICALP 90, LNCS 443, pages 322–225, 1990.Google Scholar
  4. 4.
    R. Alur. Techniques for Automatic Verification of Real-Time Systems. Technical report stan-cs-91-1378, Stanford University, 1991.Google Scholar
  5. 5.
    D. Borrione, L. Pierre, and A. Salem. PREVAIL: A proof environment for VHDL descriptions. In Proc. Advanced Research Workshop on Correct Hardware Design Methodologies, pp. 145–168, 1991.Google Scholar
  6. 6.
    C. Courcoubetis, D. Dill, M. Chatzaki, and P. Tzounakis. Verification with real-time COSPAN. In Proceedings CAV 92, 1992.Google Scholar
  7. 7.
    D. Dill. Timing assumptions and verification of finite-state concurrent systems. In Automatic Verification Methods for Finite State Systems, LNCS 407, 1989.Google Scholar
  8. 8.
    W. Damm, B. Josko, and R. Schlör. Linking VHDL with formal verification tools: How to generate finite state models out of VHDL designs. Technical report, 1992.Google Scholar
  9. 9.
    Z. Har'El and R. Kurshan. Automatic verification of coordinating systems. In Proc. Workshop on Automatic Verification Methods for Finite-State Systems, 1989.Google Scholar
  10. 10.
    T.A. Henzinger, Z. Manna, and A. Pnueli. Temporal proof methodologies for real-time systems. In Proceedings of the 18th ACM Symposium on Principles of Programming Languages, pp. 353–366, 1991.Google Scholar
  11. 11.
    IEEE standard 1076–1987, VHDL language reference manual, 1987.Google Scholar
  12. 12.
    R. Kurshan and B. Gopinath. The selection/resolution model for coordinating concurrent processes. Technical report, AT&T Bell Laboratories, 1980.Google Scholar
  13. 13.
    R. Kurshan. Analysis of discrete event coordination. LNCS 480, 1990.Google Scholar
  14. 14.
    O. Maler, Z. Manna, and A. Pnueli. From timed to hybrid systems. In [15].Google Scholar
  15. 15.
    J. W. de Bakker, C. Huizing, W.P. de Roever, and G. Rozenberg, editors. Real-Time: Theory in Practice. REX Workshop 1991. LNCS 600, 1992.Google Scholar
  16. 16.
    K.K. Sabnani, S. Aggarwal, and R.P. Kurshan. A calculus for protocol specification and validation. In Protocol Specification, Testing and Verification, III, 1983.Google Scholar
  17. 17.
    R. Schlör and W. Damm. Specification and verification of system-level hardware designs using timing diagrams. EDAC 93.Google Scholar
  18. 18.
    J. van Tassel and D. Hemmendinger. Toward formal verification of VHDL specifications. In L. Claesen, editor, Proc. Workshop on Applied Formal Methods For Correct VLSI Design, pp. 261–270, 1989.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • Costas Courcoubetis
    • 1
    • 2
  • Werner Damm
    • 3
  • Bernhard Josko
    • 3
  1. 1.Department of Computer ScienceUniversity of CreteGreek
  2. 2.Institute of Computer ScienceForthGreek
  3. 3.Department of Computer ScienceUniversity of OldenburgGermany

Personalised recommendations