A risc architecture to support neural net simulation
The Neural-RISC architecture consists of a primitive microprocessor and a parallel architecture, designed to optimise the computation of neural network models. The Neural-RISC system architecture consists of linear arrays of microprocessors connected in rings. Rings end up in an interconnecting module forming a cluster. Clusters of rings are arranged in different point-to-point topologies and are controlled by a host computer. The Neural-RISC node architecture comprises a 16-bit reduced instruction-set processor, a communication unit, and local memory—all integrated into the same silicon die. A VLSI prototype chip was implemented to demonstrate the system and node architecture. Using the standard 2μ CMOS technology, the chip integrates an array of two Neural-RISC microprocessors. This paper discusses the Neural-RISC design issues, presents a system overview and describes the VLSI implementation.
KeywordsLocal Memory Parallel Architecture VLSI Implementation Communication Unit Node Architecture
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