A risc architecture to support neural net simulation

  • Marco Pacheco
  • Philip Treleaven
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 686)


The Neural-RISC architecture consists of a primitive microprocessor and a parallel architecture, designed to optimise the computation of neural network models. The Neural-RISC system architecture consists of linear arrays of microprocessors connected in rings. Rings end up in an interconnecting module forming a cluster. Clusters of rings are arranged in different point-to-point topologies and are controlled by a host computer. The Neural-RISC node architecture comprises a 16-bit reduced instruction-set processor, a communication unit, and local memory—all integrated into the same silicon die. A VLSI prototype chip was implemented to demonstrate the system and node architecture. Using the standard 2μ CMOS technology, the chip integrates an array of two Neural-RISC microprocessors. This paper discusses the Neural-RISC design issues, presents a system overview and describes the VLSI implementation.


Local Memory Parallel Architecture VLSI Implementation Communication Unit Node Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • Marco Pacheco
    • 1
  • Philip Treleaven
    • 2
  1. 1.Departamento de Engenharia ElétricaPontificia Universidade Católica do Rio de JaneiroRJ-Rio de JaneiroBrazil
  2. 2.Department of Computer ScienceUniversity College LondonLondonUK

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