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Programmable active memories: a performance assessment

  • P. Bertin
  • D. Roncin
  • J. Vuillemin
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 678)

Abstract

We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [BRV 89]. Based on Field Programmable Gate Array (FPGA) technology, the PAM is a universal hardware co-processor closely coupled to a standard host computer. The PAM can speed up many critical software applications running on the host, by executing part of the computations through a specific hardware design. The performance measurements presented are based on two PAM architectures and ten specific applications, drawn from arithmetics, algebra, geometry, physics, biology, audio and video. Each of these PAM designs proves as fast as any reported hardware or super-computer for the corresponding application. In cases where we could bring some genuine algorithmic innovation into the design process, the PAM has proved an order of magnitude faster than any previously existing system (see [SBV 91] and [S 92]).

Keywords

Field Programmable Gate Array Digital Equipment Boltzmann Machine Maximal Clock Frequency Quantitative Performance Measurement 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • P. Bertin
    • 1
  • D. Roncin
    • 1
  • J. Vuillemin
    • 1
  1. 1.Paris Research LaboratoryDigital Equipment CorporationRueil Malmaison CedexFrance

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