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Area efficient methods to increase the reliability of circuits

  • Rüdiger Reischuk
  • Bernd Schmeltz
Parallel and Distributed Algorithms
Part of the Lecture Notes in Computer Science book series (LNCS, volume 594)

Abstract

We consider the problem to construct reliable combinatorial and clocked circuits from unreliable basic elements. The main concern in this paper is the question how such fault-tolerance increases the circuit layout. In general it requires at least a logarithmic factor increase of the number of gates. We design area efficient codes for the information transfer within a Boolean circuit. Using such a code two constructions are presented to make circuits reliable without increasing the area by a square of the redundancy overhead for their sizes. The first method splits the circuit into clusters and connects the clusters reliably by groups of wires. As an alternative, a recursive layout stratey for circuits is described which uses special graph separator properties. Under certain conditions it achieves only a constant blowup of the area compared to circuits built from completely reliable elements.

At the end we apply these methods to several well studied Boolean functions. Both constructions achieve constant area redundancy for these examples.

Keywords

Boolean Function Failure Probability Code Word Combinatorial Circuit Boolean Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1992

Authors and Affiliations

  • Rüdiger Reischuk
    • 1
  • Bernd Schmeltz
    • 1
  1. 1.Technische Hochschule DarmstadtInstitut für Theoretische InformatikDarmstadt

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