Finite state machine theory as a tool for construction of systolic arrays

  • Michael Payer
Systems Theory And CAST
Part of the Lecture Notes in Computer Science book series (LNCS, volume 410)


The goal of this paper is to exemplify a conceptual framework, namely the theory of finite state machines, for the VLSI design process. We start from a functional description of the system to be realized and achieve a (semi)systolic array in a formal way. Moreover, the resulting designs are correct by their mere construction.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    J.H. Chang, O.H. Ibarra, and M.A. Palis. Parallel parsing on a one-way array of finite-state machines. IEEE Trans. Comp., C-36(1):64–75, January 1987.Google Scholar
  2. [2]
    S.N. Cole. Real-time computation by n-dimensional iterative arrays of finite state machines. IEEE Trans. Comp., C-18(4):349–365, April 1969.Google Scholar
  3. [3]
    A. Gill. Linear Sequential Circuits. McGraw-Hill Book Company, 1966.Google Scholar
  4. [4]
    L.A. Glasser and D.W. Dobberpuhl. The Design and Analysis of VLSI Circuits. Addison-Wesley, 1985.Google Scholar
  5. [5]
    W. Grass. Some results on the design of regular structured sequential circuits. Integration, 3:189–210, 1985.Google Scholar
  6. [6]
    J. Hartmannis and R.E. Stearns. Algebraic Structure Theory of Sequential Machines. Prentice Hall, Inc., 1966.Google Scholar
  7. [7]
    O.H. Ibarra, M.A. Palis, and S.M. Kim. Designing Systolic Algorithms Using Sequential Machines. Technical Report, Universty of Minnesota, CS Dept., Inst. of Tech., 1984.Google Scholar
  8. [8]
    Z. Kohavi. Switching and Finite Automata Theory. Computer Science Series, McGraw-Hill, 1970.Google Scholar
  9. [9]
    H.T. Kung. Why systolic architectures? IEEE Computer, January 1982.Google Scholar
  10. [10]
    C.E. Leiserson. Area Efficient VLSI Computation. ACM-MIT Doctoral Dissertation Award Series, 1983.Google Scholar
  11. [11]
    C.E. Leiserson and J.B. Saxe. Optimizing synchronous systems. Journal of VLSI and Computer Systems, 1(1):41–67, 1983.Google Scholar
  12. [12]
    D.I. Moldovan. On the design of algorithms for VLSI systolic arrays. Proc. IEEE, 71(1):13–120, January 1983.Google Scholar
  13. [13]
    M. Payer. An algebraic approach to the design of pipelined sequential circuits. June 1986. Interner Bericht, FB Informatik, Universität Hamburg.Google Scholar
  14. [14]
    M. Payer. Formal derivation of systolic arrays — a case study. May 1988. International Conference on Systolic Arrays, San Diego 1988. To appear in the conference proceedings.Google Scholar
  15. [15]
    M. Payer. On systolic arrays and machine decompositions. June 1986. Interner Bericht, FB Informatik, Universität Hamburg.Google Scholar
  16. [16]
    C.H. Sequin. Managing VLSI complexity: an outlook. Proc. IEEE, 71(1):149–166, January 1983.Google Scholar
  17. [17]
    H.S. Stone. Discrete Mathematical Structures and their Applications. Science Research Associates, 1973.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1990

Authors and Affiliations

  • Michael Payer
    • 1
  1. 1.Institut für InformatikTechnische Universität MünchenMünchen 2F.R.G.

Personalised recommendations