Parallel composition of lockstep synchronous processes for hardware validation: Divide-and-conquer composition
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- Gopalakrishnan G.C., Mani N.S., Akella V. (1990) Parallel composition of lockstep synchronous processes for hardware validation: Divide-and-conquer composition. In: Sifakis J. (eds) Automatic Verification Methods for Finite State Systems. CAV 1989. Lecture Notes in Computer Science, vol 407. Springer, Berlin, Heidelberg
Consider a process M implemented as a collection of subprocesses SMi. To certify the implementation to be correct, the collective behaviors of SMi and the behavior of M are compared using a suitable verification criterion. In many approaches the implementation is specified structurally using operators such as ∥, hiding, and renaming while M is specified behaviorally using action prefixing and choice operators. This style is being used for hardware specification also [10, 8, 4, 3]. In this paper we address the question whether behavioral specifications can be deduced rapidly from structural specifications in the setting of a simple language HOP. We also address the question of doing the same for geometrically regular (array) structures that abound in VLSI. We present two algorithms PARCOMP, and PARCOMP-DC, report their performance, and explain the heuristics used to make them efficient.
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