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Code generation for a RISC machine

  • Petr Kroha
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 371)

Abstract

The algorithms of the UNIX C compiler was used to prove some properties of a Small C compiler for a RISC machine. Because of lack of the most addressing modes many tables and many procedures were becoming much more simple. The problem of data and branch conflicts we hadn't to solve because our machine doesn't use pipelining. This is due to the motivation of the machine in control of parallel processes, where the greatest part of the processor activity can be spent by waiting for an asynchronous event. That's why it didn't seem to be important to use pipelining. On examples we showed that the increase of number of instructions of the generated code when compiling a program isn't so considerable as will be usually proposed.

Keywords

Machine Instruction Register Allocation Expression Tree Direct Address Intermediate Language 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

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Copyright information

© Springer-Verlag Berlin Heidelberg 1989

Authors and Affiliations

  • Petr Kroha

There are no affiliations available

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