Advertisement

An Instruction Set Process Calculus

  • Shiu -Kai Chin
  • Jang Dae Kim
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1522)

Abstract

We have created a calculus for reasoning about hardware and firmware at the algorithmic state machine (ASM) and instructionset processor (ISP) levels of description. The calculus is a value-passing process algebra that extends the Mealy machine model to include parallel composition. It supports reasoning about the composed behavior of synchronous ASM and ISP components and microcode. We present an overview of the calculus and its application including an example showing the equivalence of a microcoded machine to its target instruction set specified by both ASM and ISP descriptions. The calculus, its properties, and the examples have been deeply embedded, proved, and verified as conservative extensions to the logic of the Higher Order Logic (HOL90) theorem prover.

Keywords

Operational Semantic Abstract Syntax Label Transition System Data Memory Memory Address 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    M. R. Barbacci. Instruction Set Processor Specifications ISPS: The Notation and its Applications. IEEE Trans. Comp., C-30(7), January 1981.Google Scholar
  2. 2.
    Thomas C. Bartee. Digital Computer Fundamentals — Sixth Edition. McGraw Hill New York, 1984.Google Scholar
  3. 3.
    Gerard Berry. The Foundations of Esterel. In G. Plotkin C. Stirling and M. Tofte, editors, Proof, Language, and Interaction: Essays in Honour of Robin Milner. MIT Press, 1998.Google Scholar
  4. 4.
    Christopher R. Clare. Designing Logic Systems Using State Machines. McGraw Hill, 1973.Google Scholar
  5. 5.
    D. Siewiorek, C. Bell, and A. Newell. Computer Structures — Principles and Examples. McGraw-Hill New York, 1982.Google Scholar
  6. 6.
    M.J.C. Gordon. A proof generating system for higher-order logic. In G. Birtwistle and P. A. Subramanyam, editors, VLSI specification, verification and synthesis. Kluwer, 1987.Google Scholar
  7. 7.
    Gordon L. Smith, Ralph Bahnsen, and Harry Halliwell. Boolean Comparison of Hardware and Flowcharts. IBM J. Res. Develop., 26(1):106–116, January 1982.Google Scholar
  8. 8.
    Z. Kohavi. Switching and Finite Automata Theory. McGraw-Hill New York, 1982.Google Scholar
  9. 9.
    T. F. Melham. A Package for Inductive Relation Definitions in HOL. In Proceedings of the 1991 International Tutorial and Workshop on the HOL Theorem Proving system. IEEE Computer Society Press, Davis, California, August 1991.Google Scholar
  10. 10.
    George Milne. Circal and the representation of communication, concurrency and time. In ACM Transactions on Programming Languages and Systems, April 1985.Google Scholar
  11. 11.
    Robin Milner. Calculi for synchrony and asynchrony. Theoretical Computer Science, 25:267–310, 1983.zbMATHCrossRefMathSciNetGoogle Scholar
  12. 12.
    Robin Milner. Communication and Concurrency. Prentice Hall, New York, 1989.zbMATHGoogle Scholar
  13. 13.
    Monica Nesi. A Formalization of the Process Algebra CCS in Higher Order Logic. Technical Report 278, University of Cambridge, December 1992.Google Scholar
  14. 14.
    Colin Stirling. Modal and Temporal Logics for Processes. In Logics for Concurrency, number 1043 in Lecture Notes in Computer Science, pages 149–237. Springer-Verlag, 1996.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Shiu -Kai Chin
    • 1
  • Jang Dae Kim
    • 2
  1. 1.National SemiconductorSanta Clara
  2. 2.EE/CS Dept.Syracuse UniversitySyracuse

Personalised recommendations