An Instruction Set Process Calculus
We have created a calculus for reasoning about hardware and firmware at the algorithmic state machine (ASM) and instructionset processor (ISP) levels of description. The calculus is a value-passing process algebra that extends the Mealy machine model to include parallel composition. It supports reasoning about the composed behavior of synchronous ASM and ISP components and microcode. We present an overview of the calculus and its application including an example showing the equivalence of a microcoded machine to its target instruction set specified by both ASM and ISP descriptions. The calculus, its properties, and the examples have been deeply embedded, proved, and verified as conservative extensions to the logic of the Higher Order Logic (HOL90) theorem prover.
KeywordsOperational Semantic Abstract Syntax Label Transition System Data Memory Memory Address
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