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Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution

  • Robert B. Jones
  • Jens U. SkakkebÆk
  • David L. Dill
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1522)

Abstract

Several methods have recently been proposed for verifying processors with out-of-order execution. These methods use intermediate abstractions to decompose the verification process into smaller steps. Unfortunately, the process of manually creating intermediate abstractions is very laborious. We present an approach that dramatically reduces the need for an intermediate abstraction, so that only the scheduling logic of the implementation is abstracted. After the abstraction, we apply an enhanced incremental-flushing approach to verify the remaining circuitry by comparing the processor description against itself in a slightly simpler configuration. By induction, we demonstrate that any reachable configuration is equivalent to the simplest possible configuration. Finally, we prove correctness on the simplest configuration. The approach is illustrated with a simple example of an out-of-order execution core.

Keywords

Schedule Algorithm Reachable State Proof Obligation Instruction Sequence Choice Sequence 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Robert B. Jones
    • 1
    • 2
  • Jens U. SkakkebÆk
    • 1
  • David L. Dill
    • 1
  1. 1.Computer Systems LaboratoryStanford UniversityStanfordUSA
  2. 2.Strategic CAD LabsHillsboroUSA

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