# Microprocessor Verification Using Efficient Decision Procedures for a Logic of Equality with Uninterpreted Functions

## Abstract

Modern processors have relatively simple specifications based on their instruction set architectures. Their implementations, however, are very complex, especially with the advent of performance-enhancing techniques such as pipelining, superscalar operation, and speculative execution. Formal techniques to verify that a processor implements its instruction set specification could yield more reliable results at a lower cost than the current simulation-based verification techniques used in industry.

The logic of equality with uninterpreted functions (EUF) provides a means of abstracting the manipulation of data by a processor when verifying the correctness of its control logic. Using a method devised by Burch and Dill [BD94], the correctness of a processor can be inferred by deciding the validity of a formula in EUF describing the comparative effect of running one clock cycle of processor operation to that of executing a small number (based on the processor issue rate) of machine instructions.

This paper describes recent advances in reducing formulas in EUF to propositional logic. We can then use either Binary Decision Diagrams (BDDs) or satisfiability procedures to determine whether this propositional formula is a tautology. We can exploit characteristics of the formulas generated when modeling processors to significantly reduce the number of propositional variables, and consequently the complexity, of the verification task.

## Keywords

Decision Procedure Propositional Logic Function Symbol Domain Variable Data Symbol## Preview

Unable to display preview. Download preview PDF.

## References

- Ack54.W. Ackermann,
*Solvable Cases of the Decision Problem*, North-Holland, Amsterdam, 1954.zbMATHGoogle Scholar - BDL96.C. Barrett, D. Dill, and J. Levitt, “Validity checking for combinations of theories with equality,”
*Formal Methods in Computer-Aided Design (FMCAD’ 96)*, M. Srivas and A. Camilleri,*eds.*, LNCS 1166, Springer-Verlag, November, 1996, pp. 187–201.CrossRefGoogle Scholar - BF89.S. Bose, and A. L. Fisher, “Verifying Pipelined Hardware Using Symbolic Logic Simulation,”
*International Conference on Computer Design (ICCD’ 89)*, 1989, pp. 217–221.Google Scholar - Bry86.R. E. Bryant, “Graph-based algorithms for Boolean function manipulation”,
*IEEE Transactions on Computers*, Vol. C-35, No. 8 (August, 1986), pp. 677–691.CrossRefGoogle Scholar - BGV99a.R. E. Bryant, S. German, and M. N. Velev, “Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic,” Technical report CMU-CS-99-115, Carnegie Mellon University, 1999. Available electronically as: http://www.cs.cmu.edu/~bryant/pubdir/cmu-cs-99-115.ps.
- BGV99b.R. E. Bryant, S. German, and M. N. Velev, “Exploiting positive equality in a logic of uninterpreted functions with equality,”
*Computer-Aided Verification (CAV’ 99)*, 1999.Google Scholar - BD94.J. R. Burch, and D. L. Dill, “Automated verification of pipelined microprocessor control,”
*Computer-Aided Verification (CAV’ 94)*, D. L. Dill,*ed.*, LNCS 818, Springer-Verlag, June, 1994, pp. 68–80.Google Scholar - Bur96.J. R. Burch, “Techniques for verifying superscalar microprocessors,”
*33rd Design Automation Conference (DAC’ 96)*, June, 1996, pp. 552–557.Google Scholar - GSZAS98.A. Goel, K. Sajid, H. Zhou, A. Aziz, and V. Singhal, “BDD based procedures for a theory of equality with uninterpreted functions,”
*Computer-Aided Verification (CAV’ 98)*, A. J. Hu and M. Y. Vardi,*eds.*, LNCS 1427, Springer-Verlag, June, 1998, pp. 244–255.CrossRefGoogle Scholar - HP96.J. L. Hennessy, and D. A. Patterson,
*Computer Architecture: A Quantitative Approach*, 2nd edition Morgan-Kaufmann, San Francisco, 1996.zbMATHGoogle Scholar - Hoa72.C. A. R. Hoare, “Proof of Correctness of Data Representations,”
*Acta Informatica*Vol. 1, 1972, pp. 271–281.zbMATHCrossRefGoogle Scholar - KN96.M. Kantrowitz, and L. M. Noack, “I’m Done Simulating; Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor,”
*33rd Design Automation Conference (DAC’ 96)*, 1996, pp. 325–330.Google Scholar - NO80.G. Nelson, and D. C. Oppen, “Fast decision procedures based on the congruence closure,”
*J. ACM*, Vol. 27, No. 2 (1980), pp. 356–364.zbMATHCrossRefMathSciNetGoogle Scholar - NJB97.K. L. Nelson, A. Jain, and R. E. Bryant, “Formal Verification of a Superscalar Execution Unit,”
*34th Design Automation Conference (DAC’ 97)*, June, 1997.Google Scholar - PRSS99.A. Pnueli, Y. Rodeh, O. Shtrichman, and M. Siegel, “Deciding equality formulas by small-domain instantiations,”
*Computer-Aided Verification (CAV’ 99)*, 1999.Google Scholar - Sho79.R. E. Shostak, “A practical decision procedure for arithmetic with function symbols,”
*J. ACM*, Vol. 26, No. 2 (1979), pp. 351–360.zbMATHCrossRefMathSciNetGoogle Scholar - SB90.M. Srivas and M. Bickford, “Formal Verification of a Pipelined Microprocessor,”
*IEEE Software*, Vol. 7, No. 5 (Sept., 1990), pp. 52–64.CrossRefGoogle Scholar - VB98.M. N. Velev, and R. E. Bryant, “Bit-level abstraction in the verification of pipelined microprocessors by correspondence checking.”
*Formal Methods in Computer-Aided Design (FMCAD’ 98)*, G. Gopalakrishnan and P. Windley,*eds.*, LNCS 1522, Springer-Verlag, November, 1998, pp. 18–35.CrossRefGoogle Scholar