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Latency Insensitive Protocols

  • Luca P. Carloni
  • Kenneth L. McMillan
  • Alberto L. Sangiovanni-Vincentelli
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1633)

Abstract

The theory of latency insensitive design is presented as the foundation of a new correct by construction methodology to design very large digital systems by assembling blocks of Intellectual Properties. Latency insensitive designs are synchronous distributed systems and are realized by assembling functional modules exchanging data on communication channels according to an appropriate protocol. The goal of the protocol is to guarantee that latency insensitive designs composed of functionally correct modules, behave correctly independently of the wire delays. A latency-insensitive protocol is presented that makes use of relay stations buffering signals propagating along long wires. To guarantee correct behavior of the overall system, modules must satisfy weak conditions. The weakness of the conditions makes our method widely applicable.

Keywords

Clock Cycle Relay Station Lexicographic Order Functional Block Trace Theory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. [1]
    L. P. Carloni, K. L. McMillan, and Alberto L. Sangiovanni-Vincentelli. Latency-Insensitive Protocols. Technical Report UCB/ERL M99/11, Electronics Research Lab, University of California, Berkeley, CA 94720, February 1999.Google Scholar
  2. [2]
    D. Matzke. Will Physical Scalability Sabotage Performance Gains? IEEE Computer, 8(9):37–39, September 1997.Google Scholar
  3. [3]
    D.L. Dill. Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits. The MIT Press, Cambridge, Mass., 1988. An ACM Distinguished Dissertation 1988.Google Scholar
  4. [4]
    T.A. Henzinger, S. Qadeer, and R.K. Rajamani. You Assume, We Guarantee: Methodology and Case Studies. In Proceedings of the 10th International Conference on Computer-Aided Verification, Vancouver, Canada, July 1998.Google Scholar
  5. [5]
    E. A. Lee and A. Sangiovanni-Vincentelli. A Framework for Comparing Models of Computation. IEEE Transactions on Computer-Aided Design, 17(12):1217–1229, December 1998.CrossRefGoogle Scholar
  6. [6]
    K. L. McMillan. A Compositional Rule for Hardware Design Refinement. In Proceedings of the 9th International Conference on Computer-Aided Verification, Haifa, Israel, July 1997.Google Scholar
  7. [7]
    J. L. A. van de Snepscheut. Trace Theory and VLSI Design, volume 200 of Lecture Notes in Computer Science. Springer Verlag, Berlin, 1985.zbMATHGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • Luca P. Carloni
    • 1
  • Kenneth L. McMillan
    • 2
  • Alberto L. Sangiovanni-Vincentelli
    • 1
  1. 1.University of California at BerkeleyBerkeley
  2. 2.Cadence Berkeley LaboratoriesBerkeley

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