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Cache coherence verification with TLA%

  • Homayoon Akhiani
  • Damien Doligez
  • Paul Harter
  • Leslie Lamport
  • Joshua Scheid
  • Mark Tuttle
  • Yuan Yu
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1709)

Abstract

We used the specification language TLA+ to analyze the correctness of two cache-coherence protocols for shared-memory multiprocessors based on two generations (EV6 and EV7) of the Alpha processor. A memory model defines the relationship between the values written by one processor and the values read by another, and a cache-coherence protocol manipulates the caches to preserve this relationship. The cache-coherence protocol is a fundamental component of any shared-memory multiprocessor design. Proving that the coherence protocol implements the memory model is a high-leverage application of formal methods. The analysis of the first protocol was largely a research project, but the analysis of the second protocol was a part of the engineers’ own verification process.

Keywords

Model Checker Formal Method State Sequence Specification Language Memory Model 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • Homayoon Akhiani
    • 1
  • Damien Doligez
    • 1
  • Paul Harter
    • 1
  • Leslie Lamport
    • 1
  • Joshua Scheid
    • 1
  • Mark Tuttle
    • 1
  • Yuan Yu
    • 1
  1. 1.Compaq Computer CorporationUK

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