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Implementation of Givens QR-Decomposition in FPGA

  • Anatoli Sergyienko
  • Oleg Maslennikov
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2328)

Abstract

A new parallel processor structure for Givens QR-decomposition intended for the FPGA implementation is presented. The structure is derived using method of mapping regular algorithms using affine transformations of the algorithm graph. The method supports pipelined processor unit design, and provides efficient hardware utilization. An example of the implementation of this structure in the Xilinx Virtex FPGA devices is presented.

Keywords

Field Programmable Gate Array Systolic Array Algorithm Graph Processor Array Twiddle Factor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Anatoli Sergyienko
    • 1
  • Oleg Maslennikov
    • 2
  1. 1.Department of Computer ScienceNational Technical University of UkraineKievUkraine
  2. 2.Technical University of KoszalinKoszalinPoland

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