Performance Optimization of 3D Multigrid on Hierarchical Memory Architectures

  • Markus Kowarschik
  • Ulrich Rüde
  • Nils Thürey
  • Christian Weiß
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2367)

Abstract

Today’s computer architectures employ fast cache memories in order to hide both the low main memory bandwidth and the latency of main memory accesses, which is slow in contrast to the floating-point performance of the CPUs. Efficient program execution can only be achieved, if the codes respect the hierarchical memory design. Iterative methods for linear systems of equations are characterized by successive sweeps over data sets, which are much too large to fit in cache. Standard implementations of these methods thus do not perform efficiently on cache-based machines. In this paper we present techniques to enhance the cache utilization of multigrid methods on regular mesh structures in 3D as well as various performance results. Most of these techniques extend our previous work on 2D problems.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Markus Kowarschik
    • 1
  • Ulrich Rüde
    • 1
  • Nils Thürey
    • 1
  • Christian Weiß
    • 2
  1. 1.Lehrstuhl für Systemsimulation (Informatik 10) Institut für InformatikFriedrich-Alexander-Universität Erlangen-NürnbergGermany
  2. 2.Lehrstuhl für Rechnertechnik und Rechnerorganisation (LRR-TUM) Fakultät für InformatikTechnische Universität MünchenGermany

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