Soft Scheduling for Hardware

  • Richard Sharp
  • Alan Mycroft
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2126)


Hardware designs typically combine parallelism and resource-sharing; a circuit’s correctness relies on shared resources being accessed mutually exclusively. Conventional high-level synthesis systems guarantee mutual exclusion by statically serialising access to shared resources during a compile-time process called scheduling. This approach suffers from two problems: (i) there is a large class of practical designs which cannot be scheduled statically; and (ii) a statically fixed schedule removes some opportunities for parallelism leading to less efficient circuits.

This paper surveys the expressivity of current scheduling methods and presents a new approach which alleviates the above problems: first scheduling logic is automatically generated to resolve contention for shared resources dynamically; then static analysis techniques remove redundant scheduling logic.

We call our method Soft Scheduling to highlight the analogy with Soft Typing: the aim is to retain the flexibility of dynamic scheduling whilst using static analysis to remove as many dynamic checks as possible.


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  1. 1.
    Aldrich, J., Chambers, C., Sirer, E., Eggers, S. Static Analyses for Eliminating Unnecessary Synchronization from Java Programs. Proceedings of the International Symposium on Static Analysis 1999. LNCS Vol. 1694, Springer Verlag.Google Scholar
  2. 2.
    Berkel, K. van. Handshake Circuits: an Asynchronous Architecture for VLSI Programming. International Series on Parallel Computation, Vol. 5. Published by Cambridge University Press, 1993.Google Scholar
  3. 3.
    Burstall, R.M. and Darlington, J. A Transformation System for Developing Recursive Programs, JACM 24(1).Google Scholar
  4. 4.
    Cartwright, R. and Fagan, M. Soft Typing. Proceedings of the ACM SIGPLAN 1991 Conference on Programming Language Design and ImplementationGoogle Scholar
  5. 5.
    De Micheli, G., Ku, D., Mailhot, F., Truong, T. The Olympus Synthesis System for Digital Design. IEEE Design & Test Magazine, October 1990.Google Scholar
  6. 6.
    De Micheli, G. Synthesis and Optimization of Digital Circuits. Published by McGraw-Hill Inc., 1994.Google Scholar
  7. 7.
    Edwards, D., Bardsley, A. Balsa 3.0 User Manual. Available from
  8. 8.
    Hennessy, J., Patterson, D. Computer Architecture A Quantitative Approach. Published by Morgan Kaufmann Publishers, Inc. (1990); ISBN 1-55860-069-8Google Scholar
  9. 9.
    IEEE. Verilog HDL Language Reference Manual. IEEE Draft Standard 1364, October 1995.Google Scholar
  10. 10.
    Ku, D., De Micheli, G. Relative Scheduling Under Timing Constraints: Algorithms for High-Level Synthesis of Digital Circuits. IEEE Transactions on CAD/ICAS, June 1992.Google Scholar
  11. 11.
    Ku, D., De Micheli, G. HardwareC—a language for hardware design (version 2.0). Stanford University Technical Report No. CSL-TR-90-419.Google Scholar
  12. 12.
    Ku, D., De Micheli, G. Constrained Resource Sharing and Conflict Resolution in Hebe. Integration-The VLSI Journal, December 1991.Google Scholar
  13. 13.
    Milner, R., Tofte, M., Harper, R. and MacQueen, D. The Definition of Standard ML (Revised). MIT Press, 1997.Google Scholar
  14. 14.
    Milner, R. The Polyadic π-calculus: a tutorial. Technical Report ECS-LFCS-91-180, Laboratory for Foundations of Computer Science, University of Edinburgh, October 1991.Google Scholar
  15. 15.
    Mycroft, A. and Sharp, R. A Statically Allocated Parallel Functional Language. Proc. of the International Conference on Automata, Languages and Programming 2000. LNCS Vol. 1853, Springer-Verlag.CrossRefGoogle Scholar
  16. 16.
    Mycroft, A. and Sharp, R. Hardware/Software Co-Design Using Functional Languages. Proc. of Tools and Algorithms for the Construction and Analysis of Systems 2001. LNCS Vol. 2031, Springer-Verlag.CrossRefGoogle Scholar
  17. 17.
    Page, I. and Luk, W. Compiling Occam into Field-Programmable Gate Arrays. In Moore and Luk (eds.) FPGAs, pages 271–283. Abingdon EE&CS Books, 1991.Google Scholar
  18. 18.
    Sharp, R. and Mycroft, A. The FLaSH Compiler: Efficient Circuits from Functional Specifications. AT&T Technical Report tr.2000.3. Available from
  19. 19.
    Sharp, R. and Mycroft, A. A Higher Level Language For Hardware Synthesis. To appear: Proc. of Correct Hardware Design and Verification Methods (CHARME), 2001.Google Scholar
  20. 20.
    Tenison Tech EDA. CtoV Reference Manual. Available from

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Richard Sharp
    • 1
    • 2
  • Alan Mycroft
    • 1
  1. 1.Computer LaboratoryCambridge UniversityCambridgeUK
  2. 2.AT&T Laboratories CambridgeCambridgeUK

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