Formalising UML State Machines for Model Checking

  • Johan Lilius
  • Iván Porres Paltor
Conference paper

DOI: 10.1007/3-540-46852-8_31

Part of the Lecture Notes in Computer Science book series (LNCS, volume 1723)
Cite this paper as:
Lilius J., Paltor I.P. (1999) Formalising UML State Machines for Model Checking. In: France R., Rumpe B. (eds) «UML»’99 — The Unified Modeling Language. UML 1999. Lecture Notes in Computer Science, vol 1723. Springer, Berlin, Heidelberg

Abstract

The paper discusses a complete formalisation of UML state machine semantics. This formalisation is given in terms of an operational semantics and it can be used as the basis for code-generation, simulation and verification tools for UML Statecharts diagrams. The formalisation is done in two steps. First, the structure of a UML state machine is translated into a term rewriting system. In the second step, the operational semantics of state machines is defined. In addition, some problematic situations that may arise are discussed. Our formalisation is able to deal with all the features of UML state machines and it has been implemented in the vUML tool, a tool for model-checking UML models.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • Johan Lilius
    • 1
  • Iván Porres Paltor
    • 1
  1. 1.Turku Centre for Computer Science (TUCS)TurkuFinland

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