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Symbolic Reachability Analysis Based on SAT-Solvers

  • Parosh Aziz Abdulla
  • Per Bjesse
  • Niklas Eén
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1785)

Abstract

The introduction of symbolic model checking using Binary Decision Diagrams (BDDs) has led to a substantial extension of the class of systems that can be algorithmically verified. Although BDDs have played a crucial role in this success, they have some well-known drawbacks, such as requiring an externally supplied variable ordering and causing space blowups in certain applications. In a parallel development, SAT-solving procedures, such as Stålmarck’s method or the Davis-Putnam procedure, have been used successfully in verifying very large industrial systems. These efforts have recently attracted the attention of the model checking community resulting in the notion of bounded model checking. In this paper, we show how to adapt standard algorithms for symbolic reachability analysis to work with SAT-solvers. The key element of our contribution is the combination of an algorithm that removes quantifiers over propositional variables and a simple representation that allows reuse of subformulas. The result will in principle allow many existing BDD-based algorithms to work with SAT-solvers. We show that even with our relatively simple techniques it is possible to verify systems that are known to be hard for BDD-based model checkers.

Keywords

Model Check Binary Decision Diagram Reachability Analysis Symbolic Model Check Reachability Problem 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. AH97.
    H. R. Andersen and H. Hulgaard. Boolean expression diagrams. In Proc. 12th IEEE Int. Symp. on Logic in Computer Science, pages 88–98, 1997. 413, 424Google Scholar
  2. BCC+99._A. Biere, A. Cimatti, E. M. Clarke, M. Fujita, and Y. Zhu. Symbolic model checking using SAT procedures instead of BDDs. In Design Automation Conference (DAC’99), 1999. 412Google Scholar
  3. BCCZ99.
    A. Biere, A. Cimatti, E. M. Clarke, and Y. Zhu. Symbolic model checking without BDDs. In Proc. TACAS’ 98, 8th Int. Conf. on Tools and Algorithms for the Construction and Analysis of Systems, 1999. 412Google Scholar
  4. BCMD92.
    J.R. Burch, E.M. Clarke, K.L. McMillan, and D.L. Dill. Symbolic model checking: 1020 states and beyond. Information and Computation, 98:142–170, 1992. 411zbMATHCrossRefMathSciNetGoogle Scholar
  5. BCRZ99.
    A. Biere, E. M. Clarke, R. Raimi, and Y. Zhu. Verifying safety properties of a PowerPC[tm] microprocessor using symbolic model checking without BDDs. In Proc. 11th Int. Conf. on Computer Aided Verification, 1999. 412Google Scholar
  6. Bje99.
    P. Bjesse. Symbolic model checking with sets of states represented as formulas. Technical Report CS-1999-100, Department of Computer Science, Chalmers technical university, March 1999. 412, 424Google Scholar
  7. Bor97.
    A. Borälv. The industrial success of verification tools based on Stålmarck’s method. In Proc. 9th Int. Conf. on Computer Aided Verification, volume 1254 of Lecture Notes in Computer Science, pages 7–10, 1997. 412Google Scholar
  8. Bor98.
    A. Borälv. Case study: Formal verification of a computerized railway interlocking. Formal Aspects of Computing, 10(4):338–360, 1998. 412zbMATHCrossRefGoogle Scholar
  9. Bry86.
    R.E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Trans. on Computers, C-35(8):677–691, Aug. 1986. 411CrossRefGoogle Scholar
  10. CES86.
    E.M. Clarke, E.A. Emerson, and A.P. Sistla. Automatic verification of finite-state concurrent systems using temporal logic specification. ACM Trans. on Programming Languages and Systems, 8(2):244–263, April 1986. 411zbMATHCrossRefGoogle Scholar
  11. Eén99.
    N. Eén. Symbolic reachability analysis based on SAT-solvers. Master’s thesis, Dept. of Computer Systems, Uppsala university, 1999. 412, 420Google Scholar
  12. GvVK95.
    J.F. Groote, S.F.M. van Vlijmen, and J.W.C. Koorn. The safety guaranteeing system at station Hoorn-Kersenboogerd. In COMPASS’95, 1995. 412Google Scholar
  13. HWA97.
    H. Hulgaard, P.F. Williams, and H.R. Andersen. Combinational logic-level verification using boolean expression diagrams. In 3rd International Workshop on Applications of the Reed-Muller Expansion in Circuit Design, 1997. 413, 424Google Scholar
  14. McM93.
    K.L. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, 1993. 411Google Scholar
  15. Pap94.
    C. Papadimitriou. Computational complexity. Addison-Wesley, 1994. 412Google Scholar
  16. QS82.
    J.P. Queille and J. Sifakis. Specification and verification of concurrent systems in Cesar. In 5th International Symposium on Programming, Turin, volume 137 of Lecture Notes in Computer Science, pages 337–352. Springer Verlag, 1982. 411Google Scholar
  17. SS90.
    G. Stålmarck and M. Säflund. Modelling and verifying systems and software in propositional logic. In SAFECOMP’90, pages 31–36. Pergamon Press, 1990. 412Google Scholar
  18. SS00.
    M. Sheeran and G. Stålmarck. A tutorial on Stålmarck’s method of propositional proof. Formal Methods In System Design, 16(1), 2000. 412Google Scholar
  19. Stå.
    G. Stålmarck. A system for determining propositional logic theorems by applying values and rules to triplets that are generated from a formula. Swedish Patent No. 467 076 (approved 1992), US patent No. 5 276 897 (1994), European Patent No. 0403 454 (1995). 412Google Scholar
  20. Zha97.
    H. Zhang. SATO: an efficient propositional prover. In Proc. Int. Conference om Automated Deduction (CADE’97), volume 1249 of LNAI, pages 272–275. Springer Verlag, 1997. 412Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Parosh Aziz Abdulla
    • 1
  • Per Bjesse
    • 2
  • Niklas Eén
    • 2
  1. 1.Uppsala University and Prover TechnologySweden
  2. 2.Chalmers University of TechnologySweden

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