A Library of Parameterized Floating-Point Modules and Their Use

  • Pavle Belanović
  • Miriam Leeser
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2438)


We present a parameterized floating-point library for use with reconfigurable hardware. Our format is both general and flexible. All IEEE formats are a subset of our format, as are all previously published floating-point formats for reconfigurable hardware. We have developed a library of fully parameterized hardware modules for format control, arithmetic operations and conversion to and from any fixed-point format. The format converters allow for hybrid implementations that combine both fixed and floating-point calculations. This permits the designer to choose between the increased range of floating-point and the increased precision of fixed-point within the same application. We illustrate the use of this library with a hybrid implementation of the K-means clustering algorithm applied to multispectral satellite images.


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  1. [1]
    IEEE Standards Board and ANSI. IEEE Standard for Binary Floating-Point Arithmetic, 1985. IEEE Std 754–1985.Google Scholar
  2. [2]
    J. Dido, N. Geraudie, L. Loiseau, O. Payeur, Y. Savaria, and D. Poirier. A Flexible Floating-Point Format for Optimizing Data-Paths and Operators in FPGA Based DSPs. In International Symposium on Field-Programmable Gate Arrays, pages 50–55. ACM, ACM Press, February 2002.Google Scholar
  3. [3]
    M. Estlick, M. Leeser, J. Theiler, and J. Szymanski. Algorithmic transformations in the implementation of k-means clustering on reconfigurable hardware. In International Symposium on Field-Programmable Gate Arrays, pages 103–110. ACM, February 2001.Google Scholar
  4. [4]
    B. Fagin and C. Renard. Field Programmable Gate Arrays and Floating Point Arithmetic. IEEE Transactions on VLSI Systems, 2(3), September 1994.Google Scholar
  5. [5]
    W. B. Ligon III, S. McMillan, G. Monn, K. Schoonover, F. Stivers, and K. D. Underwood. A Re-evaluation of the Practicality of Floating-Point Operations on FPGAs. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, April 1998.Google Scholar
  6. [6]
    L. Louca, T. A. Cook, and W. H. Johnson. Implementation of IEEE Single Precision Floating Point Addition and Multiplication on FPGAs. In K. L. Pocek and J. Arnold, editors, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pages 107–116, April 1996.Google Scholar
  7. [7]
    I. Sahin, C. S. Gloster, and C. Doss. Feasibility of Floating-Point Arithmetic in Reconfigurable Computing Systems. In 2000 MAPLD International Conference, 2000.Google Scholar
  8. [8]
    N. Shirazi, A. Walters, and P. Athanas. Quantitative Analysis of Floating Point Arithmetic on FPGA Based Custom Computing Machines. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, April 1995.Google Scholar
  9. [9]
    I. Stamoulis, M. White, and P. F. Lister. Pipelined Floating-Point Arithmetic Optimized for FPGA Architectures. In 9th International Workshop on Field Programmable Logic and Applications, volume 1673 of LNCS, pages 365–370, August-September 1999.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Pavle Belanović
    • 1
  • Miriam Leeser
    • 1
  1. 1.Department of Electrical and Computer EngineeringNortheastern UniversityBostonUSA

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