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An FPGA Based SHA-256 Processor

  • Kurt K. Ting
  • Steve C. L. Yuen
  • K. H. Lee
  • Philip H. W. Leong
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2438)

Abstract

The design, implementation and system level performance of an efficient yet compact field programmable gate array (FPGA) based Secure Hash Algorithm 256 (SHA-256) processor is presented. On a Xilinx Virtex XCV300E-8 FPGA, the SHA-256 processor utilizes 1261 slices and has a throughput of 87 MB/s at 88 MHz. When measured on actual hardware operating at 66 MHz, it had a maximum measured system throughput of 53 MB/s.

Keywords

Field Programmable Gate Array Compression Function Message Block Field Programmable Gate Array Implementation Message Schedule 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Kurt K. Ting
    • 1
  • Steve C. L. Yuen
    • 1
  • K. H. Lee
    • 1
  • Philip H. W. Leong
    • 1
  1. 1.Dept. of Computer Science and EngineeringThe Chinese University of Hong KongNew TerritoriesHong Kong

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