Fast RNS FPL-based Communications Receiver Design and Implementation

  • J. Ramírez
  • A. García
  • U. Meyer-Baese
  • A. Lloris
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2438)

Abstract

Currently, several design barriers inhibit the implementation of high-precision digital signal processing (DSP) systems with field programmable logic (FPL) devices. A new demonstration of the synergy between the residue number system (RNS) and FPL technology is presented in this paper. The quantifiable benefits of this approach are studied in the context of a high-end communications digital receiver. A new RNS-based direct digital synthesizer (DDS) that does not need a scaler circuit is introduced. The programmable decimation FIR filter is based on the arithmetic benefits associated with Galois fields and supports tuning the IF frequency as well as its bandwidth. Results show the proposed methodology requires fewer resources than classical designs, while throughput advantage is about 65%.

Keywords

Digital Signal Processing Residue Number System Galois Field Digital Receiver Direct Digital Synthesizer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • J. Ramírez
    • 1
  • A. García
    • 1
  • U. Meyer-Baese
    • 2
  • A. Lloris
    • 1
  1. 1.Dept. of Electronics and Computer TechnologyCampus Universitario FuentenuevaGranadaSpain
  2. 2.Dept. of Electrical and Computer EngineeringFlorida State UniversityTallahasseeUSA

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