Fast RNS FPL-based Communications Receiver Design and Implementation

  • J. Ramírez
  • A. García
  • U. Meyer-Baese
  • A. Lloris
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2438)


Currently, several design barriers inhibit the implementation of high-precision digital signal processing (DSP) systems with field programmable logic (FPL) devices. A new demonstration of the synergy between the residue number system (RNS) and FPL technology is presented in this paper. The quantifiable benefits of this approach are studied in the context of a high-end communications digital receiver. A new RNS-based direct digital synthesizer (DDS) that does not need a scaler circuit is introduced. The programmable decimation FIR filter is based on the arithmetic benefits associated with Galois fields and supports tuning the IF frequency as well as its bandwidth. Results show the proposed methodology requires fewer resources than classical designs, while throughput advantage is about 65%.


Digital Signal Processing Residue Number System Galois Field Digital Receiver Direct Digital Synthesizer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    Graychip, Inc., “GC1012A Digital Tuner Data Sheet”,, Feb. 1998.
  2. [2]
    Intersil, Corp., “HSP50306 Digital QPSK Demodulator”,, 1998.
  3. [3]
    Pentek, Inc., “Model 4272-Multiband Digital Receiver”,
  4. [4]
    Altera, Corp., “APEX 20K Programmable Logic Device Family Data Sheet”,, Dec. 2001, v. 4.2.
  5. [5]
    Xilinx, Inc., “Virtex 2.5V Field Programmable Gate Arrays Data Sheet”, Jul. 2001, v. 2.6.
  6. [6]
    Altera, Corp., “Implementing FIR Filters in FLEX Devices”,, Feb. 1998, v.1.01.
  7. [7]
    Xilinx Inc., “Transposed Form FIR Filters”,, Oct. 2001, v. 1.2.
  8. [8]
    N. S. Szabo and R. I. Tanaka, Residue Arithmetic and Its Applications to Computer Technology, McGraw-Hill, NY, 1967.MATHGoogle Scholar
  9. [9]
    J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, “RNS-FPL Merged Architectures for Orthogonal DWT”, Electronics Letters, vol. 36, no. 14, pp. 1198–1199, Jul. 2000.CrossRefGoogle Scholar
  10. [10]
    W. A. Chren, “RNS-Based Enhancements for Direct Digital Frequency Synthesis”, IEEE Transactions on Circuits and Systems II, vol. 42. no. 8, pp. 516–524, Aug. 1995.MATHCrossRefGoogle Scholar
  11. [11]
    P. V. A. Mohan, “On RNS-based enhancements for direct digital frequency synthesis”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 10, pp. 988–990, Oct. 2001.CrossRefGoogle Scholar
  12. [12]
    W. Namgoong, T. H. Meng, “Direct-Conversion RF Receiver Design”, IEEE Transactions on Communications, vol. 49, no. 3, pp. 518–529, Mar. 2001.MATHCrossRefGoogle Scholar
  13. [13]
    J. Ramírez, A. García, P. G. Fernández, L. Parrilla, A. Lloris, “Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform”, in Lecture Notes in Computers Science. Field Programmable Logic: The Roadmap to Reconfigurable Computing, Springer Verlag, págs. 342–351. 2000.Google Scholar
  14. [14]
    M. A. Soderstrand, W. K. Jenkins, G. A. Jullien and F. J. Taylor, Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, 1986.Google Scholar
  15. [15]
    G. A. Jullien, “Implementation of Multiplication, Modulo a Prime Number, with Applications to Number Theoretic Transforms”, IEEE Transactions on Computers, vol. C-29, no. 10, pp. 899–905, Oct. 1980.CrossRefGoogle Scholar
  16. [16]
    D. Radhakrishnan, Y. Yuan, “Fast and Highly Compact RNS Multipliers”, International Journal of Electronics, 70, pp. 281–293, 1991.MATHCrossRefMathSciNetGoogle Scholar
  17. [17]
    Xilinx, Inc., “Direct Digital Synthesizer (DDS) V2.0”,, Nov. 2000.
  18. [18]
    J. Ramírez, U. Meyer-Bäse, “Benchmarks for Programmable FIR Filters Built in RNS-FPL Technology”, accepted in 2002 SPIE’s 16th Annual International Symposium on Aerospace/Defense Sensing, Simulation, and Controls.Google Scholar
  19. [19]
    S. Piestrak, “Design of Residue Generators and Multi-Operand Modular Adders using Carry-Save Adders”, Proc. of the 10th IEEE Symposium on Computer Arithmetic, 1991.Google Scholar
  20. [20]
    M. Griffin, M. Sousa, F. Taylor, “Efficient Scaling in the Residue Number System”, Proc. of the International Conference on Acoustics, Speech and Signal Processing, pp. 1075–1078, 1989.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • J. Ramírez
    • 1
  • A. García
    • 1
  • U. Meyer-Baese
    • 2
  • A. Lloris
    • 1
  1. 1.Dept. of Electronics and Computer TechnologyCampus Universitario FuentenuevaGranadaSpain
  2. 2.Dept. of Electrical and Computer EngineeringFlorida State UniversityTallahasseeUSA

Personalised recommendations