Fast RNS FPL-based Communications Receiver Design and Implementation
Currently, several design barriers inhibit the implementation of high-precision digital signal processing (DSP) systems with field programmable logic (FPL) devices. A new demonstration of the synergy between the residue number system (RNS) and FPL technology is presented in this paper. The quantifiable benefits of this approach are studied in the context of a high-end communications digital receiver. A new RNS-based direct digital synthesizer (DDS) that does not need a scaler circuit is introduced. The programmable decimation FIR filter is based on the arithmetic benefits associated with Galois fields and supports tuning the IF frequency as well as its bandwidth. Results show the proposed methodology requires fewer resources than classical designs, while throughput advantage is about 65%.
KeywordsDigital Signal Processing Residue Number System Galois Field Digital Receiver Direct Digital Synthesizer
Unable to display preview. Download preview PDF.
- Graychip, Inc., “GC1012A Digital Tuner Data Sheet”, http://wwws.ti.com/sc/psheets/slws128/slws128.pdf, Feb. 1998.
- Intersil, Corp., “HSP50306 Digital QPSK Demodulator”, http://www.intersil.com/data/FN/FN4/FN4162/FN4162.pdf, 1998.
- Pentek, Inc., “Model 4272-Multiband Digital Receiver”, http://www.pentek.com/products/GetDS.cfm/4272.PDF?Filename=ACF405.pdf.
- Altera, Corp., “APEX 20K Programmable Logic Device Family Data Sheet”, http://www.altera.com/literature/ds/apex.pdf, Dec. 2001, v. 4.2.
- Xilinx, Inc., “Virtex 2.5V Field Programmable Gate Arrays Data Sheet” http://www.xilinx.com/partinfo/ds003-2.pdf, Jul. 2001, v. 2.6.
- Altera, Corp., “Implementing FIR Filters in FLEX Devices”, http://www.altera.com/literature/an/an073.pdf, Feb. 1998, v.1.01.
- Xilinx Inc., “Transposed Form FIR Filters”, http://www.xilinx.com/xapp/xapp219.pdf, Oct. 2001, v. 1.2.
- J. Ramírez, A. García, P. G. Fernández, L. Parrilla, A. Lloris, “Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform”, in Lecture Notes in Computers Science. Field Programmable Logic: The Roadmap to Reconfigurable Computing, Springer Verlag, págs. 342–351. 2000.Google Scholar
- M. A. Soderstrand, W. K. Jenkins, G. A. Jullien and F. J. Taylor, Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, 1986.Google Scholar
- Xilinx, Inc., “Direct Digital Synthesizer (DDS) V2.0”, http://www.xilinx.com/ipcenter/catalog/logicore/docs/dds.pdf, Nov. 2000.
- J. Ramírez, U. Meyer-Bäse, “Benchmarks for Programmable FIR Filters Built in RNS-FPL Technology”, accepted in 2002 SPIE’s 16th Annual International Symposium on Aerospace/Defense Sensing, Simulation, and Controls.Google Scholar
- S. Piestrak, “Design of Residue Generators and Multi-Operand Modular Adders using Carry-Save Adders”, Proc. of the 10th IEEE Symposium on Computer Arithmetic, 1991.Google Scholar
- M. Griffin, M. Sousa, F. Taylor, “Efficient Scaling in the Residue Number System”, Proc. of the International Conference on Acoustics, Speech and Signal Processing, pp. 1075–1078, 1989.Google Scholar