A Comparison of Counting and Sampling Modes of Using Performance Monitoring Hardware

  • Shirley V. Moore
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2330)


Performance monitoring hardware is available on most modern microprocessors in the form of hardware counters and other registers that record data about processor events. This hardware may be used in counting mode, in which aggregate events counts are accumulated, and/or in sampling mode, in which time-based or event-based sampling is used to collect profiling data. This paper discusses uses of these two modes and considers the issues of efficiency and accuracy raised by each. Implications for the PAPI cross-platform hardware counter interface are also discussed.


Sampling Mode Data Address Data Cache Memory Hierarchy Program Counter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Browne, S., Dongarra, J., Garner, N., Ho, G., Mucci, P.: A Portable Programming Interface for Performance Evaluation on Modern Processors. International Journal of High Performance Computing Applications 14:3 (Fall 2000) 189–204.CrossRefGoogle Scholar
  2. 2.
    Browne, S., Dongarra, J., Garner, N. London, K., Mucci, P.: A Scalable Cross-Platform Infrastructure for Application Performance Optimization Using Hardware Counters. SC’2000. Dallas, Texas. November, 2000.Google Scholar
  3. 3.
    Buck, B., Hollingsworth, J.K.: Using Hardware Performance Monitors to Isolate Memory Bottlenecks. SC’2000. Dallas, Texas. November, 2000.Google Scholar
  4. 4.
    Burger, D., Austin, T. M.: The SimpleScalar Tool Set, Version 2.0. University of Wisconsin-Madison Computer Sciences Department Technical Report 1942. June, 1997.
  5. 5.
    Dean, J., Hicks, J., Waldspurger, C. A., Weihl, W. E., Chrysos, G.: ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors. 30th Symposium on Microarchitecture (Micro-30). December, 1997.Google Scholar
  6. 6.
    Dean, J., Waldspurger, C. A., Weihl, W. E.: Transparent, Low-Overhead Profiling on Modern Processors. Workshop on Profile and Feedback-Directed Compilation. Paris, France. October, 1998.Google Scholar
  7. 7.
  8. 8.
    Intel IA-64 Architecture Software Developer’s Manual, Volume 4: Itanium Processor Programmer’s Guide. Intel, July 2000.
  9. 9.
    Korn, W., Teller, P., Castillo, G.: Just how accurate are performance counters? 20th IEEE International Performance, Computing, and Communications Conference. Phoenix, Arizona. April, 2001.Google Scholar
  10. 10.
    PCL-the Performance Counter Library:
  11. 11.
    Parallel Tools Consortium:
  12. 12.
    Pressel, D.: Envelope: A New Approach to Performance Prediction. Department of Defense HPC Users Group Conference. Biloxi, Mississippi. June, 2001.Google Scholar
  13. 13.
    Origin 2000 and Onyx2 Performance Tuning and Optimization Guide. SGI Docu-ment number 007-3430-003. July, 2001.
  14. 14.
    Snavely, A., Wolter, N., Carrington, L.: Modeling Application Performance by Convolving Machine Signatures with Application Profiles. IEEE 4th Annual Workshop on Workload Characterization. Austin, Texas. December, 2001.Google Scholar
  15. 15.

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Shirley V. Moore
    • 1
  1. 1.Innovative Computing LaboratoryUniversity of TennesseeKnoxvilleUSA

Personalised recommendations