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A Pipelined Hardware Implementation of Genetic Programming Using FPGAs and Handel-C

  • Peter Martin
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2278)

Abstract

A complete Genetic Programming (GP) system implemented in a single FPGA is described in this paper. The GP system is capable of solving problems that require large populations and by using parallel fitness evaluations can solve problems in a much shorter time that a conventional GP system in software. A high level language to hardware compilation system called Handel-C is used for implementation.

Keywords

Genetic Programming Clock Cycle Field Programmable Gate Array High Level Language Parallel Evaluation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Peter Martin
    • 1
  1. 1.Department of Computer ScienceUniversity of EssexColchesterUK

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