Optimizing Static Power Dissipation by Functional Units in Superscalar Processors

  • Siddharth Rele
  • Santosh Pande
  • Soner Onder
  • Rajiv Gupta
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2304)


We present a novel approach which combines compiler, instruction set, and microarchitecture support to turn off functional units that are idle for long periods of time for reducing static power dissipation by idle functional units using power gating [2],[9]. The compiler identifies program regions in which functional units are expected to be idle and communicates this information to the hardware by issuing directives for turning units off at entry points of idle regions and directives for turning them back on at exits from such regions. The microarchitecture is designed to treat the compiler directives as hints ignoring a pair of off and on directives if they are too close together. The results of experiments show that some of the functional units can be kept off for over 90% of the time at the cost of minimal performance degradation of under 1%.


Functional Unit Basic Block Dynamic Power Superscalar Processor Power Block 
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  1. 1.
    D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In International Symposium on Computer Architecture (ISCA), pages 83–94, Vancouver, British Columbia, June 2000.Google Scholar
  2. 2.
    J. A. Butts and G. S. Sohi. A Static Power Model for Architects. In IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 191–201. December 2000.Google Scholar
  3. 3.
    C. Fraser and D. Hanson. lcc: A Retargetable C Compiler: Design and Implementation. Adison Wesley Publishing Company, 1995.Google Scholar
  4. 4.
    M. Horowitz, T. Indermaur, and R. Gonzalez. Low-Power Digital Design. In IEEE Symposium on Low Power Electronics, pages 8–11, 1994.Google Scholar
  5. 5.
    K. S. Khouri and N. K. Jha. Private Communication. June 2001.Google Scholar
  6. 6.
    C. Lee, M. Potkonjak, and W. H. Mangione-Smith. Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In IEEE/ACM International Symposium on Microarchitecture (MICRO), Research Triangle Park, North Carolina, December 1997.Google Scholar
  7. 7.
    MIPS Technologies, 1225 Charleston Road, Mountain View CA-94043. MIPS32 4k Processor Core Family, Software Users Manual, 1.12 edition, January 2001.Google Scholar
  8. 8.
    S. Onder and R. Gupta. Automatic Generation of Microarchitecture Simulators. In IEEE International Conference on Computer Languages (ICCL), pages 80–89, Chicago, Illinois, May 1998.Google Scholar
  9. 9.
    M. D. Powell, S-H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar. Gated-Vdd:a Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories. In ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2000.Google Scholar
  10. 10.
    K. Roy. Leakage Power Reduction in Low-Voltage CMOS Design. In IEEE International Conference on Circuits and Systems, pages 167–173, 1998.Google Scholar
  11. 11.
    S. Thompson, P. Packan, and M. Bohr. MOS Scaling: Transistor Challenges of the 21st Century. Intel Technology Journal, Q3, 1998.Google Scholar
  12. 12.
    V. Tiwari, R. Donnelly, S. Malik, and R. Gonzalez. Dynamic Power Management for Microprocessors: A Case Study. In International Conference on VLSI Design, pages 185–192, 1997.Google Scholar
  13. 13.
    V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. patel, and F. Baez. Reducing Power in High-Performance Processors. In Design Automation Conference (DAC), pages 732–737, 1998.Google Scholar
  14. 14.
    Q. Wang and S. Vrudhula. Static Power Optimization of Deep Submicron CMOS Circuits for Dual V T Technology. In International Conference on Computer-Aided Design (ICCAD), pages 490–496, 1998.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Siddharth Rele
    • 1
  • Santosh Pande
    • 2
  • Soner Onder
    • 3
  • Rajiv Gupta
    • 4
  1. 1.Dept of ECECSUniversity of CincinnatiCincinnati
  2. 2.College of Computing, Georgia TechAtlanta
  3. 3.Dept. of Computer ScienceMichigan Tech. Univ.Houghton
  4. 4.Dept. of Computer ScienceThe Univ.of ArizonaTucson

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