Advertisement

Formal Verification of UML Statecharts with Real-Time Extensions

  • Alexandre David
  • M. Oliver Möller
  • Wang Yi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2306)

Abstract

We present a framework for formal veri.cation of a realtime extension of UML statecharts. For clarity, we restrict ourselves to a reasonable subset of the rich UML statechart model and extend this with real-time constructs (clocks, timed guards, and invariants). We equip the obtained formalism, called hierarchical timed automata (HTA), with an operational semantics. We outline a translation of one HTA to a network of flat timed automata, that can serve as input to the real-time model checking tool Uppaal. This translation can be used to faithfully verify deadlock-freedom, safety, and unbounded response properties of the HTA model. We report on an XML-based implementation of this translation, use the well-known pacemaker example to illustrate our technique, and report run-time data for the formal verification part.

Keywords

Operational Semantic Parallel Composition Computation Tree Logic Clock Constraint Formal Syntax 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Luca Aceto and FranÇois Laroussinie. Is your Model Checker on Time? In Proc. 24th Int. Symp. Math. Found. Comp. Sci. (MFCS’99), Szklarska Poreba, Poland, Sep. 1999, volume 1672 of Lecture Notesi n Computer Science, pages 125–136. Springer-Verlag, 1999.Google Scholar
  2. 2.
    Rajeev Alur and Thomas A. Henzinger. Real-time Logics: Complexity and Expressiveness. Information and Computation, 1(104):35–77, 1993. preliminary version appeared in Proc. 5th LICS, 1990.CrossRefMathSciNetGoogle Scholar
  3. 3.
    Tobias Amnell, Gerd Behrmann, Johan Bengtsson, Pedro R. D’Argenio, Alexandre David, Ansgar Fehnker, Thomas Hune, Bertrand Jeannet, Kim G. Larsen, M. Oliver Möller, Paul Pettersson, Carsten Weise, and Wang Yi. Uppaal-Now, Next, and Future. In Proc. of the Summer School on Modelling and Verification of Parallel Processes (MOVEP’2k), Nantes, France, June 19 to 23, 2001.Google Scholar
  4. 4.
    Alexandre David and M. Oliver Möller. From HUppaal to Uppaal: A Translation from Hierarchical Timed Automata to Flat Timed Automata. Research Series RS-01-11, BRICS, Department of Computer Science, University of Aarhus, March 2001. see http://www.brics.dk/RS/01/11/.
  5. 5.
    Bruce Powel Douglass. Real-Time UML, Second Edition— Developing Efficient Objectsfo r Embedded Systems. Addison-Wesley, 1999.Google Scholar
  6. 6.
    David Harel and Eran Gery. Executable Object Modeling with Statecharts. IEEE Computer, 7(30):31–42, July 1997.Google Scholar
  7. 7.
    Klaus Havelund, Arne Skou, Kim G. Larsen, and Kristian Lund. Formal Modelling and Analysis of an Audio/Video Protocol: An Industrial Case Study Using Uppaal. In Proc. of the 18th IEEE Real-Time Systems Symposium, pages 2–13. IEEE Computer Society Press, December 1997.Google Scholar
  8. 8.
    Thomas. A. Henzinger, Xavier Nicollin, Joseph Sifakis, and Sergio Yovine. Symbolic Model Checking for Real-Time Systems. Information and Computation, 111(2):193–244, 1994.MATHCrossRefMathSciNetGoogle Scholar
  9. 9.
    Gerand J. Holzmann. The Model Checker SPIN. IEEE Transactions on Software Engineering, 23(5):279–295, May 1997.CrossRefMathSciNetGoogle Scholar
  10. 10.
    Thomas S. Hune, Judi Romijn, Mariëlle Stoelinga, and Frits W. Vaandrager. Linear parametric model checking of timed automata. Research Series RS-01-5, BRICS, Department of Computer Science, University of Aarhus, January 2001. 44 pp.Google Scholar
  11. 11.
    Paul Pettersson Kim G. Larsen and Wang Yi. Model-Checking for Real-Time Systems. In Proc. of the 10th International Conference on Fundamentalsof Computation Theory, volume 965 of Lecture Notes in Computer Science, pages 62–88. Springer-Verlag, 1995.Google Scholar
  12. 12.
    Kim G. Larsen, Paul Pettersson, and Wang Yi. Uppaal in a Nutshell. Int. Journal on Software Tools for Technology Transfer, 1(1–2):134–152, October 1997.MATHCrossRefGoogle Scholar
  13. 13.
    Johan Lilius and Ivan Porres. Formalising UML State Machines for Model Checking. In UML’99— The Unified Modeling Language, volume 1723 of Lecture Notes in Computer Science, pages 430–445. Springer-Verlag, October 1999.CrossRefGoogle Scholar
  14. 14.
    Magnus Lindahl, Paul Pettersson, and Wang Yi. Formal Design and Analysis of a Gear Controller. In Proc. of the 4th International Workshop on Tools and Algorithms for the Construction and Analysis of Systems., volume 1384 of Lecture Notesin Computer Science, pages 281–297. Springer-Verlag, 1998.Google Scholar
  15. 15.
    Henrik Lönn and Paul Pettersson. Formal Verification of a TDMA Protocol Start-Up Mechanism. In Proc. of IEEE Pacific Rim International Symposium on Fault-Tolerant Systems, pages 235–242, 1997.Google Scholar
  16. 17.
    Carsta Petersohn and Luis Urbina. A timed semantics for the STATEMATE implementation of statecharts. In John Fitzgerald, Cli. B. Jones, and Peter Lucas, editors, FME’97: Industrial Applications and Strengthened Foundations of Formal Methods ( Proc. 4th Intl. Symposium of Formal Methods Europe, Graz, Austria, September 1997), volume 1313 of Lecture Notes in Computer Science, pages 553–572. Springer-Verlag, September 1997. ISBN 3-540-63533-5.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Alexandre David
    • 1
  • M. Oliver Möller
    • 2
  • Wang Yi
    • 1
  1. 1.Department of Information TechnologyUppsala UniversitySweden
  2. 2.BRICS Basic Research in Computer ScienceAarhus UniversitySweden

Personalised recommendations