Structured Scheduling of Recurrence Equations: Theory and Practice

  • Patrice Quinton
  • Tanguy Risset
Chapter
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2268)

Abstract

We present new methods for scheduling structured systems of recurrence equations. We introduce the notion of structured dependence graph and structured scheduling. We show that the scheduling of recurrence equations leads to integer linear programs whose practical complexity is O(n3), where n is the number of constraints. We give new algorithms for computing linear and multi-dimensional structured scheduling, using existing techniques for scheduling non-structured systems of affine recurrence equations. We show that structured scheduling is more than one order of magnitude more efficient than the scheduling of corresponding inlined systems.

Keyword

parallelization of loop nests structured recurrence equations scheduling automatic synthesis of parallel architectures parallel vlsi architectures 

References

  1. 1.
    Karp, R., Miller, R., Winograd, S.: The organization of computations for uniform recurrence equations. Journal of the ACM 14 (1967) 563–590MATHCrossRefMathSciNetGoogle Scholar
  2. 2.
    Lamport, L.: The Parallel Execution of DO Loops. Communications of The ACM 17 (1974) 83–93MATHCrossRefMathSciNetGoogle Scholar
  3. 3.
    Feautrier, P.: Some efficient solutions to the affine scheduling problem, part I, one dimensional time. Int. J. of Parallel Programming 21 (1992) 313–348MATHCrossRefMathSciNetGoogle Scholar
  4. 4.
    Wolf, M., Lam, M.: Loop transformation theory and an algorithm to maximize parallelism. IEEE Transactions on Parallel and Distributed Systems 2 (1991) 452–471CrossRefGoogle Scholar
  5. 5.
    Darte, A., Khachiyan, L., Robert, Y.: Linear scheduling is nearly optimal. Parallel Processing Letters 1 (1991) 73–81CrossRefGoogle Scholar
  6. 6.
    Kung, H.: Why systolic architectures? Computer 15 (1982) 37–46CrossRefGoogle Scholar
  7. 7.
    Lee, P., Kedem, Z.: Mapping nested loop algorithms into multidimensional systolic arrays. IEEE Transaction On Parallel and Distributed System 1 (90) 64–76Google Scholar
  8. 8.
    Moldovan, D.: On the analysis and synthesis of VLSI systolic arrays. IEEE Transactions on Computers 31 (1982) 1121–1126MATHCrossRefGoogle Scholar
  9. 9.
    Mauras, C., Quinton, P., Rajopadhye, S., Saouter, Y.: Scheduling affine parameterized recurrences by means of variable dependent timing functions. In Kung, S.E.E. Swartzlander, J., Fortes, J., Przytula, K., eds.: Application Specific Array Processors, IEEE Computer Society Press (1990) 100–110Google Scholar
  10. 10.
    Ashcroft, E., Wadge, W.: Lucid, a formal system for writing and proving programs. SIAM j. Comp. 3 (1976) 336–354CrossRefMathSciNetGoogle Scholar
  11. 11.
    Caspi, P., Halbwachs, N., Pilaud, D., Plaice, J.: Lustre: a declarative language for programming synchronous systems. In: 14th Symposium on Principles of Programming Languages, ACM, Munich (1987)Google Scholar
  12. 12.
    Le Guernic, P., Benveniste, A., Bournai, P., Gautier, T.: SIGNAL: A data flow oriented language for signal processing. In: IEEE Workshop on VLSI 1984. (1984)Google Scholar
  13. 13.
    Chen, M., Choo, Y., Li, J. In: Crystal: Theory and Pragmatics of Generating Efficient Parallel Code. ACM Press (1991) Chapter 7Google Scholar
  14. 14.
    Perrin, G., Genaud, S., Violard, E.: PEI: a theoretical framework for data-parallel programming. Technical report, ICPS, Strasbourg (1994)Google Scholar
  15. 15.
    Mauras, C.: Alpha: un langage équationnel pour la conception et la programmation d’architectures parallèles synchrones. Thèse de doctorat, Ifsic, Université de Rennes 1 (1989)Google Scholar
  16. 16.
    Dupont De Dinechin, F., Robert, S., Risset, T.: Structured scheduling of recurrence equations. Technical Report 1140, Irisa, Rennes, France (1997)Google Scholar
  17. 17.
    Wilde, D.: The Alpha language. Technical Report 827, Irisa, Rennes, France (1994)Google Scholar
  18. 18.
    Saouter, Y.: A propos de systèmes d’équations récurrentes. Thèse de doctorat, Ifsic, Université de Rennes 1 (1992)Google Scholar
  19. 19.
    Darte, A.: Techniques de parallélisation automatique de nids de boucles. Thèse de doctorat, LIP ENS-Lyon (1993)Google Scholar
  20. 20.
    Feautrier, P.: Some efficient solution to the affine scheduling problem, part II, multidimensional time. Int. J. of Parallel Programming 21 (1992)Google Scholar
  21. 21.
    Chaudhary, V., Xu, C.Z., Roy, S., Ju, J., Sinha, V., Luo, L.: Design and evaluation of an environment ape for automatic parallelization of programs. In: Int. Symp. on Parallel Architectures, Algorithms, and Networks. (1996) 77–83Google Scholar
  22. 22.
    Irigoin, F., Jouvelot, P., R. Triolet: Overview of the PIPS project. In: Procs of the Int. Workshop on Compiler for Parallel Computers, Paris. (1990) 199–212Google Scholar
  23. 23.
    Raji-Werth, M., Feautrier, P.: On parallel program generation for massively parallel architectures. In Durand, M., Dabaghi, F.E., eds.: High Performance Computing II, North-Holland (1991)Google Scholar
  24. 24.
    Griebl, M., Lengauer, C.: The loop parallelizer LooPo. In Gerndt, M., ed.: Proc. Sixth Workshop on Compilers for Parallel Computers. Volume 21 of Konferenzen des Forschungszentrums Jülich. Forschungszentrum Jülich (1996) 311–320Google Scholar
  25. 25.
    Burleson, W.: Using regular array methods for DSP module synthesis. In: 27th Hawaii Int. Conf. System Science Vol 1: Architecture. (1994) 58–67Google Scholar
  26. 26.
    Catthoor, F., Danckaert, K., Kulkarni, C., Omnes, T.: Data transfer and storage architecture issues and exploration in multimedia processors. In: Programmable Digital Signal Processors: Architecture, Programming, and Applications. Marcel Dekker, Inc, New York (2000)Google Scholar
  27. 27.
    Kienhuis, B., Rijpkema, E., Deprettere, E.: Compaan: Deriving process networks from matlab for embedded signal processing architectures. In: 8th International Workshop on Hardware/Software Codesign (CODES’2000). (2000)Google Scholar
  28. 28.
    Dupont de Dinechin, F., Quinton, P., Risset, S.R.T.: First steps in alpha. Publication Interne 1244, Irisa (1999)Google Scholar
  29. 29.
    De Dinechin, F.D., Quinton, P., Risset, T.: Structuration of the Alpha language. In Giloi, W., Jahnichen, S., Shriver, B., eds.: Massively Parallel Programming Models, IEEE Computer Society Press (1995) 18–24Google Scholar
  30. 30.
    Dupont De Dinechin, F.: Libraries of schedule-free operators in Alpha. In: Application Specific Array Processor. (1997)Google Scholar
  31. 31.
    Crop, J., Wilde, D.: Scheduling Structured Systems. In: Fifth International Europar Conference. LNCS, Toulouse, France, Springer Verlag (1999) 409–412Google Scholar
  32. 32.
    Darte, A., Robert, Y.: Scheduling uniform loop nests. Technical Report 92-10, Laboratoire de l’Informatique du Parallélisme, Ecole Normale Supérieure de Lyon, France (1992)Google Scholar
  33. 33.
    Feautrier, P.: Parametric integer programming. RAIRO Recherche Opérationnelle 22 (1988) 243–268MATHMathSciNetGoogle Scholar
  34. 34.
    Schrijver, A.: Theory of Linear and Integer Programming. John Wiley and Sons, New York (1986)MATHGoogle Scholar
  35. 35.
    Darte, A., Vivien, F.: Revisiting the decomposition of Karp, Miller and Winograd. In: Application Specific Array Processor. (1997) 13–25Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Patrice Quinton
    • 1
  • Tanguy Risset
    • 2
  1. 1.IrisaRennes CedexFrance
  2. 2.LIPENS LyonLyon Cedex 07

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