Design Tools for Application Specific Embedded Processors

  • Wei Qin
  • Subramanian Rajagopalan
  • Manish Vachharajani
  • Hangsheng Wang
  • Xinping Zhu
  • David August
  • Kurt Keutzer
  • Sharad Malik
  • Li-Shiuan Peh
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2491)

Abstract

A variety of factors make it increasingly difficult and expensive to design and manufacture traditional Application Specific Integrated Circuits (ASICs). Consequently, programmable alternatives are more attractive than ever. The flexibility provided by programmability comes with a performance and power overhead. This can be significantly mitigated by using application specific platforms, also referred to as Application Specific Embedded Processors, or Application Specific Instruction Set Processors (ASIPs).

ASIPs and the embedded software applications running on them, require specialized design tools - both during architectural evaluation to provide feedback on the suitability of the architecture for the application; as well as during system implementation to ensure efficient mapping and validation of design constraints. These functions result in requirements different from those of traditional software development environments. The first requirement is retargetability, especially during the early architectural evaluation stage where a rapid examination of design alternatives is essential. The second requirement is for additional metrics such as power consumption, real-time constraints and code size.

This paper describes a set of design tools and associated methodology designed to meet the challenges posed by architectural evaluation and software synthesis. This work is part of the MESCAL (Modern Embedded Systems, Compilers, Architectures, and Languages) project1.

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References

  1. 1.
    Paulin, P.: What is the next EDA driver? Design Automation Conference Panel (2002)Google Scholar
  2. 2.
    Pai, V.S., Ranganathan, P., Adve, S.V.: RSIM reference manual, version 1.0. Technical Report 9705, Department of Electrical and Computer Engineering, Rice University (1997)Google Scholar
  3. 3.
    Vachharajani, M., Vachharajani, N., Penry, D., Blome, J., August, D.: Architectural exploration with Liberty. Technical Report Liberty-02-01, Liberty Research Group, Princeton University (2002)Google Scholar
  4. 4.
    The Liberty Research Group: http://liberty.princeton.edu/ (2002)
  5. 5.
    Kiczales, G., Lamping, J., Menhdhekar, A., Maeda, C., Lopes, C., Loingtier, J.M., Irwin, J.: Aspect-oriented programming. In: Proceedings of the 11th European Conference on Object-Oriented Programming. (1997) 220–242Google Scholar
  6. 6.
    SystemC Community: http://www.systemc.org (2002)
  7. 7.
    IBM Corp.: The CoreConnectTM bus architecture. Technical White Paper (1999)Google Scholar
  8. 8.
    ARM Holdings PLC: Advanced microcontroller bus architecture (AMBA) specification rev 2.0. http://www.arm.com/ Documentation/UserMans/AMBA (2001)
  9. 9.
    Dally, W.J., Towles, B.: Route packet, not wires: On-chip interconnection networks. In: Proceedings of Design Automation Conference. (2001)Google Scholar
  10. 10.
    Sgroi, M., Sheets, M., Mihal, A., Keutzer, K., Malik, S., Rabaey, J., Sangiovanni-Vincentelli, A.: Addressing the system-on-a-chip interconnect woes through communication-based design. In: Proceedings of Design Automation Conference. (2001)Google Scholar
  11. 11.
    Taylor, M.B., et. al.: The Raw microprocessor: A computational fabric for software circuits and general-purpose programs. IEEE Micro 22 (2002)Google Scholar
  12. 12.
    Rumbaugh, J., Blaha, M., Premerlani, W., Eddy, F., Lorensen, W.: Object-Oriented Modeling and Design. Prentice-Hall, New York, NY (1991)Google Scholar
  13. 13.
    Davis, J., et. al.: Ptolemy II-heterogeneous concurrent modeling and design in Java. Technical Report UCB/ERL M01/12, Dep. of EECS, Univ. of California at Berkeley (2001)Google Scholar
  14. 14.
    Zhu, X., Malik, S.: A hierarchical modeling framework for on-chip communication architectures. In: Proceedings of International Conference on Computer-Aided Design. (2002)Google Scholar
  15. 15.
    Katevenis, M., Vatsolaki, P., Efthymiou, A.: Pipelined memory shared buffer for VLSI switches. In: Proceedings of Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication. (1995)Google Scholar
  16. 16.
    Yang, X., Lee, R.B.: Fast subword permutation instructions using omega and flip network stages. In: Proceedings of International Conference on Computer Design. (2000)Google Scholar
  17. 17.
    Wang, H.S., Zhu, X.P., Peh, L.S., Malik, S.: Orion: A dynamic power simulator for interconnection networks-enabling power-performance tradeoffs for emerging microprocessor systems. Technical Report PU-02-06, Department of Electrical Engineering, Princeton University (2002)Google Scholar
  18. 18.
    Peh, L.S., Dally, W.J.: A delay model and speculative architecture for pipelined routers. In: Proceedings of International Symposium on High-Performance Computer Architecture. (2001)Google Scholar
  19. 19.
    Wang, H.S., Peh, L.S., Malik, S.: A power model for routers: Modeling Alpha 21364 and InfiniBand routers. In: Proceedings of Hot Interconnects 10. (2002)Google Scholar
  20. 20.
    Qin, W.: Mescal architecture description. http://www.ee.princeton.edu/~mescal/mad.html (2002)
  21. 21.
    Zimmerman, G.: The MIMOLA design system: a computer aided processor design method. In: Proceedings of Design Automation Conference. (1979) 53–58Google Scholar
  22. 22.
    Freericks, M.: The nML machine description formalism. Technical Report 1991/15, Technische Universität Berlin, Fachbereich Informatik, Berlin, DE (1991)Google Scholar
  23. 23.
    Hadjiyiannis, G., Hanono, S., Devadas, S.: ISDL: An instruction set description language for retargetability. In: Proceedings of Design Automation Conference. (1997) 299–302Google Scholar
  24. 24.
    Pees, S., Hoffmann, A., Zivojnovic, V., Meyr, H.: LISA-machine description language for cycle-accurate models of programmable DSP architectures. In: Proceedings of Design Automation Conference. (1999) 933–938Google Scholar
  25. 25.
    Halambi, A., Grun, P., Ganesh, V., Khare, A., Dutt, N., Nicolau, A.: EXPRESSION: A language for architecture exploration through compiler/simulator retargetability. In: Proceedings of Conference on Design Automation and Test in Europe. (1999) 485–490Google Scholar
  26. 26.
    Paakki, J.: Attribute grammar paradigms-a high-level methodology in language implementation. ACM Computing Surveys 27 (1995) 196–255CrossRefGoogle Scholar
  27. 27.
    ARM Ltd.: ARM architecture reference manual. http://www.arm.com/arm/ documentation (1996)
  28. 28.
    Rajagopalan, S., Vachharajani, M., Malik, S.: Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. In: Proceedings of International Conference on Compilers, Architectures and Synthesis for Embedded Systems. (2000)Google Scholar
  29. 29.
    Bradlee, D.G., Henry, R.R., Eggers, S.J.: The marion system for retargetable instruction scheduling. In: Proceedings of Conference on Programming Language Design and Implementation. (1991) 229–240Google Scholar
  30. 30.
    Chen, K., Malik, S., August, D.I.: Retargetable static timing analysis for embedded software. In: Proceedings of International Symposium on System Synthesis. (2001)Google Scholar
  31. 31.
    Fraser, C.W., Hanson, D.R.: A Retargetable C Compiler: Design and Implementation. Addison-Wesley, Menlo Park, CA (1995)MATHGoogle Scholar
  32. 32.
    Triantafyllis, S., Vachharajani, M., August, D.: The Liberty Compiler intermediate representation. Technical Report Liberty-02-02, Liberty Research Group, Princeton University (2002)Google Scholar
  33. 33.
    Marwedel, P., Goossens, G.: Code Generation for Embedded Processors. Kluwer Academic Publishers (1995)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Wei Qin
    • 1
  • Subramanian Rajagopalan
    • 1
  • Manish Vachharajani
    • 1
  • Hangsheng Wang
    • 1
  • Xinping Zhu
    • 1
  • David August
    • 1
  • Kurt Keutzer
    • 2
  • Sharad Malik
    • 1
  • Li-Shiuan Peh
    • 1
  1. 1.Princeton UniversityPrincetonUSA
  2. 2.UC BerkeleyBerkeleyUSA

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