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Verification of Timed Automata via Satisfiability Checking

  • Peter Niebert
  • Moez Mahfoudh
  • Eugene Asarin
  • Marius Bozga
  • Oded Maler
  • Navendu Jain
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2469)

Abstract

In this paper we show how to translate bounded-length verification problems for timed automata into formulae in difference logic, a propositional logic enriched with timing constraints. We describe the principles of a satisfiability checker specialized for this logic that we have implemented and report some preliminary experimental results.

Keywords

Boolean Variable Satisfying Assignment Symbolic Model Check Bound Model Check Time Automaton 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Peter Niebert
    • 2
  • Moez Mahfoudh
    • 1
  • Eugene Asarin
    • 1
  • Marius Bozga
    • 1
  • Oded Maler
    • 1
  • Navendu Jain
    • 3
  1. 1.VERIMAGGiéresFrance
  2. 2.Laboratoire d’Informatique FondamentaleCMIMarseille Cedex 13France
  3. 3.Computer Science and Eng. Dept.Indian Inst. of TechnologyNew DelhiIndia

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