A Cache Simulator for Shared Memory Systems

  • Florian Schintke
  • Jens Simon
  • Alexander Reinefeld
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2074)


Due to the increasing gap between processor speed and memory access time, a large fraction of a program’s execution time is spent in accesses to the various levels in the memory hierarchy. Hence, cache-aware programming is of prime importance. For efficiently utilizing the memory subsystem, many architecture-specific characteristics must be taken into account: cache size, replacement strategy, access latency, number of memory levels, etc.

In this paper, we present a simulator for the accurate performance prediction of sequential and parallel programs on shared memory systems. It assists the programmer in locating the critical parts of the code that have the greatest impact on the overall performance. Our simulator is based on the Latency-of-Data-Access Model that focuses on the modeling of the access times to different memory levels.

We describe the design of our simulator, its configuration and its usage in an example application.


Memory Access Cache Size Access Latency Memory Hierarchy Share Memory System 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    James R. Larus and and Eric Schnarr. EEL: Machine-independent executable editing. In Proceedings of the SIGPLAN’95 Conference on Programming Language Design and Implementation, pages 291–300, 1995.Google Scholar
  2. 2.
    Davor Magdic. Limes: A multiprocessor environment for PC Platforms. In IEEE Computer Society Technical Committee on Computer Architecture Newsletter, March 1997.Google Scholar
  3. 3.
    Larry McVoy and Carl Staelin. lmbench: portable tools for performance analysis. In USENIX 1996 Annual Technical Conference, January 22-26, 1996. San Diego, CA, USA, pages 279–294, Berkeley, CA, USA, January 1996. USENIX.Google Scholar
  4. 4.
    Shubhendu S. Mukherjee, Steven K. Reinhardt, Babak Falsafi, Mike Litzkow, Mark D. Hill, David A. Wood, Steven Huss-Lederman, and James R. Larus. Wisconsin Wind Tunnel II: A fast, portable parallel architecture simulator. IEEE Concurrency, 8(4):12–20, October/December 2000.CrossRefGoogle Scholar
  5. 5.
    OMG. Unified Modeling Language Specification. Open Management Group, Version 1.3 edition, June 1999.Google Scholar
  6. 6.
    Vijay S. Pai, Parthasarathy Ranganathan, and Serita V. Adve. RSIM: An Execution-Driven Simulator for IPL-Based Shared-Memory Multiprocessors and Uniprocessors. In IEEE Computer Society Technical Committee on Computer Architecture Newsletter, March 1997.Google Scholar
  7. 7.
    M. Prvulović, D. Marinov, Z. Dimitrijević, and V. Milutinović. Split Temporal/Spatial Cache: A Survey and Reevaluation of Performance. In IEEE Computer Society Technical Committee on Computer Architecture Newsletter, July 1999.Google Scholar
  8. 8.
    Florian Schintke. Ermittlung von Programmlaufzeiten anhand von Speicherzugriffen, Microbenchmarks und Simulation von Speicherhierarchien. Technical Report ZR-00-33, Konrad-Zuse-Zentrum für Informationstechnik Berlin (ZIB), 2000.Google Scholar
  9. 9.
    Jens Simon and Jens-Michael Wierum. The Latency-of-Data-Access Model for Analyzing Parallel Computation. Information Processing Letters, 66(5):255–261, June 1998.CrossRefGoogle Scholar
  10. 10.
    Edward Tam, Jude Rivers, Gary Tyson, and Edward S. Davidson. mlcache: A flexible multi-lateral cache simulator. Technical Report CSE-TR-363-98, Computer Science and Engineering, University of Michigan, May 1998.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Florian Schintke
  • Jens Simon
  • Alexander Reinefeld

There are no affiliations available

Personalised recommendations