A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems

  • Daniel González
  • Antonio García
  • Graham A. Jullien
  • Javier Ramírez
  • Luis Parrilla
  • Antonio Lloris
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2451)

Abstract

Synchronization of VLSI systems is growing in complexity because of the increase in die size and integration levels, along with stronger requirements for integrated circuit speed and reliability. The size increase leads to delays and synchronization losses in clock distribution. Additionally, the large amount of synchronous hardware in integrated circuits requires large current spikes to be drawn from the power supply when the clock changes state. This paper presents a new approach for clock distribution in RNS-based systems, where channel independence removes clock timing restrictions. This approach generates several clock signals with non-overlapping edges from a global clock. This technique shows a significant decrease in instantaneous current requirements and a homogeneous time distribution of current supply to the chip, while keeping extra hardware to a minimum and introducing an affordable power cost, as shown through simulation.

Keywords

Clock Signal Solid State Circuit Residue Number System Master Clock Current Spike 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    J. Yuan and C. Svensson, “High-speed CMOS Circuit Technique”, IEEE Journal of Solid State Circuits, vol 24, no. 1, pp. 62–70, Jan. 1989.CrossRefGoogle Scholar
  2. 2.
    D. W. Bailey and B. J. Benchsneider, “Clocking Design and Analysis for a 600-MHz Alpha Microprocessor”, IEEE Journal of Solid State Circuits, vol 33, pp.1627–1633, Dec 1998.Google Scholar
  3. 3.
    P. Ramanathan, A. J. Dupont and K. G. Shin, “Clock Distribution in General VLSI Circuits.” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol 41, no. 5, pp. 395–404, May 1994.CrossRefGoogle Scholar
  4. 4.
    J. Yoo, G. Gopalakrishnan and K. F. Smith, “Timing Constraints for High-speed Counterflow-clocked Pipelining”, IEEE Transactions on VLSI Systems, vol. 7, no. 2, pp. 167–173, Jun. 1999.CrossRefGoogle Scholar
  5. 5.
    E. B. Hogenauer, “An Economical Class of Digital Filters for Decimation and Interpolation”, IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 29,no. 2, pp. 155–162, Feb. 1981.CrossRefGoogle Scholar
  6. 6.
    U. Meyer-Bäse, A. Garcia and F. J. Taylor, “Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic”, Journal of VLSI Signal Processing, vol. 28, no. 1/2, pp. 115–128, May 2001.MATHCrossRefGoogle Scholar
  7. 7.
    N. S. Szabo and R. I. Tanaka, Residue Arithmetic and Its Applications to Computer Technology, McGraw-Hill, NY, 1967.MATHGoogle Scholar
  8. 8.
    M. A. Soderstrand, W. K. Jenkins, G. A. Jullien and F. J. Taylor, Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, 1986.Google Scholar
  9. 9.
    W. D. Grover, “A New Method for Clock Distribution.” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol 41, no. 2, pp. 149–160, Feb. 1994.CrossRefGoogle Scholar
  10. 10.
    M. A. B. Jackson, A. Srinivasan and E. S. Kuh, “Clock Routing for High Performance IC’s” 27 th ACM/IEEE Design Automation Conference, 1990.Google Scholar
  11. 11.
    D. F. Wann and N. A. Franklin, “Asynchronous and Clocked Control Structures for VLSI Based Interconnect Networks”, IEEE Transactions on Computers, vol 32, no.5, pp. 284–293, May 1983.CrossRefGoogle Scholar
  12. 12.
    E. G. Friedman, “Clock Distribution Networks in Synchronous Digital Integrated Circuits”. Proceedings of the IEEE, vol. 89, no. 5, pp. 665–692, May 2001.Google Scholar
  13. 13.
    E. G. Friedman and S. Powell, “Design and Analysis of an Hierarchical Clock Distribution System for Synchronous Cell/macrocell VLSI”, IEEE Journal of Solid State Circuits, vol. 21, no. 2, pp., 240–246, Apr. 1986.CrossRefGoogle Scholar
  14. 14.
    M. Shoji, “Elimination of Process-dependent Clock skew in CMOS VLSI“. IEEE Journal of Solid State Circuits, vol. 21, pp. 869–880, Oct. 1986.CrossRefGoogle Scholar
  15. 15.
    MOSIS Process Information, “Hewlett Packard AMOS14TB”, http://www.mosis.org/technical/processes/proc-hp-amos14tb.html

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Daniel González
    • 1
  • Antonio García
    • 1
  • Graham A. Jullien
    • 2
  • Javier Ramírez
    • 1
  • Luis Parrilla
    • 1
  • Antonio Lloris
    • 1
  1. 1.Dpto. Electrónica y Tecnología de ComputadoresUniversidad de GranadaGranadaSpain
  2. 2.ATIPS Laboratory, Dept. of Electrical and Computer EngineeringUniversity of CalgaryCalgaryCanada

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