Verification Using Test Generation Techniques

  • Vlad Rusu
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2391)

Abstract

Applying formal methods to testing has recently become a popular research topic. In this paper we explore the opposite approach, namely, applying testing techniques to formal verification. The idea is to use symbolic test generation to extract subgraphs (called components) from a specification and to perform the verification on the components rather than on the whole system. This may considerably reduce the verification effort and, under reasonable sufficient conditions, a safety property verified on a component also holds on the whole specification. We demonstrate the approach by verifying an electronic purse system using our symbolic test generation tool STG and the PVS theorem prover.

Keywords

Formal verification conformance testing electronic purse 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Vlad Rusu
    • 1
  1. 1.IRISA/INRIARennesFrance

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