Extracting Exact Time Bounds from Logical Proofs

  • Mauro Ferrari
  • Camillo Fiorentini
  • Mario Ornaghi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2372)


Accurate evaluation of delays of combinatorial circuits is crucial in circuit verification and design. In this paper we present a logical approach to timing analysis which allows us to compute exact stabilization bounds while proving the correctness of the boolean behavior.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    D.A. Basin and N. Klarlund. Automata based symbolic reasoning in hardware verification. Formal Methods in Systems Design, 13(3):255–288, 1998.CrossRefGoogle Scholar
  2. 2.
    J. Brzozowski and M. Yoeli. Ternary simulation of binary gate networks. In J. M. Dunn and G. Epstein, editors, Modern Uses of Multiple-Valued Logic, pages 41–50. D. Reidel, 1977.Google Scholar
  3. 3.
    A. Chagrov and M. Zakharyaschev. Modal Logic. Oxford University Press, 1997.Google Scholar
  4. 4.
    C.T. Gray, W. Liu, R.K. CavinIII, and H.-Y. Hsieh. Circuit delay calculation considering data dependent delays. INTEGRATION, The VLSI Journal, 17:1–23, 1994.CrossRefGoogle Scholar
  5. 5.
    S. Malik. Analysis of Cyclic Combinational Circuits. In IEEE /ACM International Conference on CAD, pages 618–627. ACM/IEEE, IEEE Computer Society Press, 1993.Google Scholar
  6. 6.
    Ju.T. Medvedev. Interpretation of logical formulas by means of finite problems and its relation to the realizability theory. Soviet Mathematics Doklady, 4:180–183, 1963.MATHGoogle Scholar
  7. 7.
    M. Mendler. A timing refinement of intuitionistic proofs and its application to the timing analysis of combinational circuits. In P. Miglioli, U. Moscato, D. Mundici, and M. Ornaghi, editors, Proceedings of the 5th International Workshop on Theorem Proving with Analytic Tableaux and Related Methods, pages 261–277. Springer, LNAI 1071, 1996.Google Scholar
  8. 8.
    M. Mendler. Characterising combinational timing analyses in intuitionistic modal logic. Logic Journal of the IGPL, 8(6):821–852, 2000.MATHCrossRefMathSciNetGoogle Scholar
  9. 9.
    M. Mendler. Timing analysis of combinational circuits in intuitionistic propositional logic. Formal Methods in System Design, 17(1):5–37, 2000.CrossRefGoogle Scholar
  10. 10.
    P. Miglioli, U. Moscato, M. Ornaghi, S. Quazza, and G. Usberti. Some results on intermediate constructive logics. Notre Dame Journal of Formal Logic, 30(4):543–562, 1989.MATHCrossRefMathSciNetGoogle Scholar
  11. 11.
    P. Miglioli, U. Moscato, M. Ornaghi, and G. Usberti. A constructivism based on classical truth. Notre Dame Journal of Formal Logic, 30(1):67–90, 1989.MATHCrossRefMathSciNetGoogle Scholar
  12. 12.
    D. Prawitz. Natural Deduction. Almquist and Winksell, 1965.Google Scholar
  13. 13.
    R.H. Thomason. A semantical study of constructible falsity. Zeitschrift für Mathematische Logik und Grundlagen der Mathematik, 15:247–257, 1969.MATHMathSciNetCrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Mauro Ferrari
    • 1
  • Camillo Fiorentini
    • 1
  • Mario Ornaghi
    • 1
  1. 1.Dipartimento di Scienze dell’InformazioneUniversità degli Studi di MilanoItaly

Personalised recommendations