Extracting Exact Time Bounds from Logical Proofs

  • Mauro Ferrari
  • Camillo Fiorentini
  • Mario Ornaghi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2372)

Abstract

Accurate evaluation of delays of combinatorial circuits is crucial in circuit verification and design. In this paper we present a logical approach to timing analysis which allows us to compute exact stabilization bounds while proving the correctness of the boolean behavior.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Mauro Ferrari
    • 1
  • Camillo Fiorentini
    • 1
  • Mario Ornaghi
    • 1
  1. 1.Dipartimento di Scienze dell’InformazioneUniversità degli Studi di MilanoItaly

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