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Buffer Size Requirements for Delay Sensitive Traffic Considering Discrete Effects and Service-Latency in ATM Switches

  • Steven Wright
  • Yannis Viniotis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1815)

Abstract

Various approaches to buffer size and management for output buffering in ATM switches supporting delay sensitive traffic are reviewed. Discrete worst case arrival and service functions are presented. Using this format, bounds are developed for buffer size under zero cell loss for leaky bucket constrained sources. Tight bounds are developed for the case of discrete arrival functions with fluid servers and fluid arrival functions with discrete servers. A bound on the buffer size is also proposed for the case of discrete arrival and service process. While this bound is not exact, the maximum gain that could be achieved by a tighter bound is bounded. In some cases it is possible to reduce the buffer size requirements through over allocation of link bandwidth. Feasibility conditions for this scenario are developed.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Steven Wright
    • 1
  • Yannis Viniotis
    • 2
  1. 1.BellSouth Science & Technology, 41G70 BSCAtlantaUSA
  2. 2.Dept. ECENorth Carolina State UniversityRaleighUSA

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