Second Generation Delay Model for Submicron CMOS Process

  • M. Rezzoug
  • P. Maurine
  • D. Auvergne
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1918)

Abstract

The performance characterization and optimization of logic circuits under rapid process migration is one of the big challenges of nowadays submicron CMOS technologies. This characterization must be robust on a wide design space in predicting the performance evolution of designs. In this paper we present a second generation of analytical modeling of delay performance, considering speed carrier desaturation induced non linear variation of delay, I/O coupling, load and input ramp effects. A first model is deduced for inverters and then extended to logic gates through a reduction protocol of the serial transistor array. Validations are given, on a 0.18μm process, by comparing values of simulated (HSPICE) and calculated delay for different configurations of inverters and gates.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • M. Rezzoug
    • 1
  • P. Maurine
    • 1
  • D. Auvergne
    • 1
  1. 1.LIRMM, UMR CNRSUniversité de Montpellier II, (C5506)MontpellierFrance

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