Second Generation Delay Model for Submicron CMOS Process
The performance characterization and optimization of logic circuits under rapid process migration is one of the big challenges of nowadays submicron CMOS technologies. This characterization must be robust on a wide design space in predicting the performance evolution of designs. In this paper we present a second generation of analytical modeling of delay performance, considering speed carrier desaturation induced non linear variation of delay, I/O coupling, load and input ramp effects. A first model is deduced for inverters and then extended to logic gates through a reduction protocol of the serial transistor array. Validations are given, on a 0.18μm process, by comparing values of simulated (HSPICE) and calculated delay for different configurations of inverters and gates.
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- 2.L. Bisdounis, S. Nikolaidis, O. Koufopavlou “Propagation Delay and Short-Circuit Power Dissipation Modelling of the C.M.O.S. Inverter”, IEEE Transactions on Circuits and Systems-I:Fundamental Theory and Applications, Vol. 45, n° 3, March 1998.Google Scholar
- 4.T. Sakurai and A. R. Newton, “Alpha-power model, and its application to CMOS inverter delay and other formulas”, IEEE JSSC vol. 25, pp 584–594, April 1990.Google Scholar
- 8.A. Chatzigeorgiou, S. Nikolaidis “Collapsing the Transistor Chain to an Effective Single Equivalent Transistor” DATE’98, pp. 2–6, Paris. March 1998.Google Scholar
- 11.Ph. Maurine, M. Rezzoug, D. Auvergne “Design Oriented Modeling of Short Circuit Power Dissipation for Submicronic CMOS” pp645–650. DCIS’99. November 1999.Google Scholar