Second Generation Delay Model for Submicron CMOS Process

  • M. Rezzoug
  • P. Maurine
  • D. Auvergne
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1918)


The performance characterization and optimization of logic circuits under rapid process migration is one of the big challenges of nowadays submicron CMOS technologies. This characterization must be robust on a wide design space in predicting the performance evolution of designs. In this paper we present a second generation of analytical modeling of delay performance, considering speed carrier desaturation induced non linear variation of delay, I/O coupling, load and input ramp effects. A first model is deduced for inverters and then extended to logic gates through a reduction protocol of the serial transistor array. Validations are given, on a 0.18μm process, by comparing values of simulated (HSPICE) and calculated delay for different configurations of inverters and gates.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    J. T. Kong and D. Overhauser, “Methods to Improve Digital MOS Macromodel Accuracy”, IEEE Trans. on CAD of ICs and systems, vol. 14, no. 7, pp.868–881 July 1995.CrossRefGoogle Scholar
  2. 2.
    L. Bisdounis, S. Nikolaidis, O. Koufopavlou “Propagation Delay and Short-Circuit Power Dissipation Modelling of the C.M.O.S. Inverter”, IEEE Transactions on Circuits and Systems-I:Fundamental Theory and Applications, Vol. 45, n° 3, March 1998.Google Scholar
  3. 3.
    T. Sakurai and A. Richard Newton, “Delay Analysis of Series-Connected MOSFET Circuits”, IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, Feb. 1991, pp 122–131.CrossRefGoogle Scholar
  4. 4.
    T. Sakurai and A. R. Newton, “Alpha-power model, and its application to CMOS inverter delay and other formulas”, IEEE JSSC vol. 25, pp 584–594, April 1990.Google Scholar
  5. 5.
    A. Nabavi_Lishi, N. C. Rumin “Inverter models of CMOS gates for supply current and delay evaluation”, IEEE trans. On CAD of Integrated Circuits and systems, vol.13, n° 10, pp.1271–1279, 1994.CrossRefGoogle Scholar
  6. 6.
    K.O. Jeppson, “Modeling the influence of the transistor gain ratio and the input to output coupling capacitance on the CMOS inverter delay”, IEEE J.Solid State Circuits, vol. 29, n° 6, pp. 646–654, June 1994.CrossRefGoogle Scholar
  7. 7.
    A. Hirata, H. Onodera, K. Tamaru “Estimation of Propagation Delay Considering Short Circuit Current for Static CMOS Gates”. IEEE Transactions. On Circuits and Systems-I-, vol.45, n° 11, pp.1194–1198, November 1998.CrossRefGoogle Scholar
  8. 8.
    A. Chatzigeorgiou, S. Nikolaidis “Collapsing the Transistor Chain to an Effective Single Equivalent Transistor” DATE’98, pp. 2–6, Paris. March 1998.Google Scholar
  9. 9.
    J. M. Daga, D. Auvergne “A comprehensive delay macromodeling for submicron CMOS logics” IEEE J. of Solid State Circuits Vol. 34n° 1, Jan 1999, pp 42–56.CrossRefGoogle Scholar
  10. 10.
    A.I. Kayssi, K.A. Sakallah and T. Mudge, “The impact of signal transition time on path delay computation” IEEE Trans. on Circuits and Systems II: analog and digital processing, vol.40, n° 5, pp.302–309, May 1993.MATHCrossRefGoogle Scholar
  11. 11.
    Ph. Maurine, M. Rezzoug, D. Auvergne “Design Oriented Modeling of Short Circuit Power Dissipation for Submicronic CMOS” pp645–650. DCIS’99. November 1999.Google Scholar
  12. 12.
    S. Turgis, D. Auvergne “A novel macromodel for power estimation for CMOS structures” IEEE Trans. On CAD of integrated circuits and systems vol.17, n° 11, pp1090–1098, nov.1998.CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • M. Rezzoug
    • 1
  • P. Maurine
    • 1
  • D. Auvergne
    • 1
  1. 1.LIRMM, UMR CNRSUniversité de Montpellier II, (C5506)MontpellierFrance

Personalised recommendations