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A Genetic Algorithm for VLSI Floorplanning

  • Christine L. Valenzuela
  • Pearl Y. Wang
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1917)

Abstract

We present a genetic algorithm (GA) which uses a normalized postfix encoding scheme to solve the VLSI floorplanning problem. We claim to have overcome the representational problems previously associated with encoding postfix expressions into GAs, and have developed a novel encoding system which preserves the integrity of solutions under all the genetic operators. Optimal floorplans are obtained for module sets taken from some MCNC benchmarks. The slicing tree construction process, used by our GA to generate the floorplans, has a run time scaling which compares very favourably with other recent approaches.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Christine L. Valenzuela
    • 1
  • Pearl Y. Wang
    • 2
  1. 1.Department of Computer ScienceCardiff UniversityCardiffUK
  2. 2.Department of Computer Science MS4A5George Mason UniversityFairfaxUSA

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