Advertisement

Approximation of Worst-Case Execution Time for Preemptive Multitasking Systems

  • Matteo Corti
  • Roberto Brega
  • Thomas Gross
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1985)

Abstract

The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler’s admission tests and subsequently limits a task’s execution time during operation. If a task exceeds theWCET, this situation is detected and either a handler is invoked or control is transferred to a human operator. Such control systems usually support preemptive multitasking, and if an object-oriented programming language (e.g., Java, C++, Oberon) is used, then the system may also provide dynamic loading and unloading of software components (modules). Only modern, state-of-the art microprocessors can provide the necessary compute cycles, but this combination of features (preemption, dynamic un/loading of modules, advanced processors) creates unique challenges when estimating the WCET. Preemption makes it difficult to take the state of the caches and pipelines into account when determining the WCET, yet for modern processors, a WCET based on worst-case assumptions about caches and pipelines is too large to be useful, especially for big and complex real-time products. Since modules can be loaded and unloaded, each task must be analyzed in isolation, without explicit reference to other tasks that may execute concurrently.

Keywords

Execution Time Basic Block Instruction Cache Execution Unit Performance Monitor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    P. Altenbernd. On the false path problem in hard real-time programs. In Proc. 8th Euromicro Workshop on Real-Time Systems, pages 102–107, L’Aquila, Italy, June 1996.Google Scholar
  2. [2]
    R. Brega. A real-time operating system designed for predictability and run-time safety. In Proc. 4th Int. Conf. Motion and Vibration Control (MOVIC), pages 379–384, Zurich, Switzerland, August 1998. ETH Zurich.Google Scholar
  3. [3]
    J. Busquets-Mataix and A. Wellings. Adding instruction cache effect to schedulability analysis of preemptive real-time systems. In Proc. 8th Euromicro Workshop on Real-Time Systems, pages 271–276, L’Aquila, June 1996.Google Scholar
  4. [4]
    C.-S. Cheng, J. Stankovic, and K. Ramamritham. Scheduling algorithms for hard real-time systems-A brief survey. In J. Stankovic and K. Ramamritham, editors, Tutorial on Hard Real-Time Systems, pages 150–173. IEEE Computer Society Press, 1988.Google Scholar
  5. [5]
    J. Dean, J. Hicks, C. Waldspurger, W. Weihl, and G. Chrysos. ProfileMe: Hardware support for instruction-level profiling on out-of-order processors. In Proc. 30th Annual IEEE/ACM Int. Symp. on Microarchitecture (MICRO-97), pages 292–302, LosAlamitos, CA, December 1997. IEEE Computer Society.Google Scholar
  6. [6]
    D. Diez and S. Vestli. D’nia an object oriented real-time system. Real-Time Magazine, (3):51–54, March 1995.Google Scholar
  7. [7]
    P. Emma. Understanding some simple processor-performance limits. IBM J. Research and Development, 43(3):215–231, 1997.Google Scholar
  8. [8]
    C. Healy, R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Trans. Computers, 48(1):53–70, January 1999.CrossRefGoogle Scholar
  9. [9]
    C. Healy, M. Sjödin, V. Rustagi, and D. Whalley. Bounding loop iterations for timing analysis. In Proc. 4th Real-Time Technology and Applications Symp., pages 12–21, Denver, Colorado, June 1998.Google Scholar
  10. [10]
    C. Healy and D. Whalley. Tighter timing predictions by automatic detection and exploitation of value-dependent constraints. In Proc. 5th Real-Time Technology and Applications Symp., pages 79–88, Vancouver, Canada, June 1999.Google Scholar
  11. [11]
    M. Honegger, R. Brega, and G. Schweitzer. Application of a nonlinear adaptive controller to a 6 dof parallel manipulator. In Proc. IEEE Int. Conf. Robotics and Automation, pages 1930–1935, San Francisco CA, April 2000. IEEE.Google Scholar
  12. [12]
    IBM Microelectronic Division and Motorola Inc. PowerPC 604/604e RISC Microprocessor User’s Manual, 1998.Google Scholar
  13. [13]
    S.-K. Kim, S. Min, and Ha R. Efficient worst case timing analysis of data caching. In Proc. 2nd 1996 IEEE Real-Time Technology and Applications Symposium, pages 230–240, Boston, MA, June 1996. IEEE.Google Scholar
  14. [14]
    D. Kirk. SMART (Strategic Memory Allocation for Real-Time) cache design. In Proc. 10th IEEE Real-Time Systems Symp., pages 229–239, Santa Monica, California, December 1989. IEEE.Google Scholar
  15. [15]
    E. Kligerman and A. Stoyenko. Real-time Euclid:A language for reliable real-time systems. IEEE Trans. on Software Eng., 12(9):941–949, September 1986.Google Scholar
  16. [16]
    L. Ko, C. Healy, E. Ratliff, R. Arnold, D. Whalley, and M. Harmon. Supporting the specification and analysis of timing constraints. In Proc. 2nd IEEE Real-Time Technology and Applications Symp., pages 170–178, Boston, MA, June 1996. IEEE.Google Scholar
  17. [17]
    C.-G. Lee, J. Hahn, Y.-M. Seo, S. Min, R. Ha, S. Hong, C. Park, M. Lee, and C. Kim. Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. In Proc. 17th IEEE Real-Time Systems Symp., pages 264–274,Washington, D.C., December 1996. IEEE.Google Scholar
  18. [18]
    F. Levine and C. Roth. A programmer’s view of performance monitoring in the PowerPC microprocessor. IBM J. Research and Development, 41(3):345–356, May 1997.CrossRefGoogle Scholar
  19. [19]
    Y.-T. Li, S. Malik, and A. Wolfe. Cache modeling for real-time software: Beyond directed mapped instructions caches. In Proc. 17th IEEE Real-Time Systems Symp., pages 254–263, Washington, D.C., December 1996. IEEE.Google Scholar
  20. [20]
    J. Liedtke, H. Härtig, and M. Hohmuth. OS-controlled cache predictability for real-time systems. In Proc. 3rd IEEE Real-Time Technology and Applications Symp., Montreal, Canada, June 1997. IEEE.Google Scholar
  21. [21]
    S.-S. Lim, Y. Bae, G. Jang, B.-D. Rhee, S. Min, C. Park, H. Shin, K. Park, S.-M. Moon, and C.-S. Kim. An accurate worst case timing analysis for RISC processors. IEEE Trans. on Software Eng., 21(7):593–604, July 1995.CrossRefGoogle Scholar
  22. [22]
    S.-S. Lim, J. Han, J. Kim, and S. Min. A worst case timing analysis technique for multipleissue machines. In Proc. 19th IEEE Real-Time Systems Symp., pages 334–345, Madrid, Spain, December 1998. IEEE.Google Scholar
  23. [23]
    A. Mok and G. Liu. Efficient runtime monitoring of timing constraints. In Proc. 3rd Real-Time Technology and Applications Symp., Montreal, Canada, June 1997.Google Scholar
  24. [24]
    H. Mössenböck and N. Wirth. The programming language Oberon-2. Structured Programming, 12(4), 1991.Google Scholar
  25. [25]
    S. Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers, 1997.Google Scholar
  26. [26]
    F. Müller and J. Wegener. A comparison of static analysis and evolutionary testing for the verification of timing constraints. In Proc. 19th Real Time Technology and Applications Symp., pages 179–188, Madrid, Spain, June 1998. IEEE.Google Scholar
  27. [27]
    C. Park. Predicting program execution times by analyzing static and dynamic program paths. Real-Time Systems, (5):31–62, 1993.Google Scholar
  28. [28]
    P. Puschner and C. Koza. Calculating the maximum execution time of real-time programs. J. Real-Time Systems, 1(2):160–176, September 1989.Google Scholar
  29. [29]
    P. Puschner and R. Nossal. Testing the results of static worst-case execution-time analysis. In Proc. 19th Real-Time Systems Symp., pages 134–143, Madrid, Spain, December 1998. IEEE.Google Scholar
  30. [30]
    P. Puschner and A. Vrchoticky. Problems in static worst-case execution time analysis. In 9. ITG/GI-Fachtagung Messung, Modellierung und Bewertung von Rechen-und Kommunikationssystemen, Kurzbeiträge und Toolbeschreibungen, pages 18–25, Freiberg, Germany, September 1997.Google Scholar
  31. [31]
    F. Stappert and P. Altenbernd. Complete worst-case execution time analysis of straight-line hard real-time programs. J. System Architecture, 46(4):339–335, April 2000.CrossRefGoogle Scholar
  32. [32]
    H. Theiling and C. Ferdinand. Combining abstract interpretation and ILP for microarchitecture modelling and program path analysis. In Proc. 19th IEEE Real-Time Systems Symp., pages 144–153, Madrid, Spain, December 1998. IEEE.Google Scholar
  33. [33]
    N. Wirth and J. Gutknecht. Project Oberon — The Design of an Operating System and Compiler. ACM Press, NewYork, 1992.Google Scholar
  34. [34]
    N. Zhang, A. Burns, and M. Nicholson. Pipelined processors and worst case execution times. Real-Time Systems, 5(4):319–343, October 1993.CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Matteo Corti
    • 1
  • Roberto Brega
    • 2
  • Thomas Gross
    • 1
  1. 1.Departement InformatikETH ZürichZürich
  2. 2.Institute of RoboticsETH ZürichZürich

Personalised recommendations