A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder

  • Peter Celinski
  • Sorin D. Cotofana
  • Derek Abbott
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2687)


A high speed 64-bit dynamic adder, the Adelaide-Delft Threshold Logic Adder (A-DELTA), is presented. The adder is based on a hybrid carry-lookahead/carry-select scheme using threshold logic and conventional CMOS logic. A-DELTA was designed and simulated in a 0.35 μm process. The worst case critical path latency is 670 ps, which is shown to be on average 30% faster than previously proposed high speed Boolean dynamic logic adders while at the same time reducing the transistor count on average by over 30% compared to the same adders.


Boolean Function Critical Path Threshold Logic Critical Path Delay Input Operand 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Peter Celinski
    • 1
    • 3
  • Sorin D. Cotofana
    • 3
  • Derek Abbott
    • 2
  1. 1.Centre for High Performance Integrated Technologies & Systems (CHiPTec)Australia
  2. 2.Centre for Biomedical Engineering, The Department of Electrical and Electronic EngineeringThe University of AdelaideSAAustralia
  3. 3.Computer Engineering Group, Electrical Engineering DepartmentDelft University of TechnologyCD DelftThe Netherlands

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