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Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines

  • João M. P. Cardoso
  • Horácio C. Neto
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

This paper presents new achievements on the automatic mapping of abstract algorithms, written in imperative software programming languages, to custom computing machines. The reconfigurable hardware element of the target architecture consists of one field-programmable gate array coupled with one or more memories. The compilation flow exposes operation- and functional-level parallelism, and speculative execution. Such expositions are efficiently represented in a hierarchical model. In order to take full advantage of such representation, the scheduling scope is significantly improved by merging basic blocks at loop boundaries and by considering the parallel execution of exposed concurrent loops. The paper describes the scheduling technique, shows a study on the impact of the merge operation, and reveals the improvements achieved when the exposed parallelism is fully satisfied.

Keywords

Parallel Execution Compilation Technique Speculative Execution Abstract Algorithm Temporal Partitioning 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • João M. P. Cardoso
    • 1
    • 3
  • Horácio C. Neto
    • 2
    • 3
  1. 1.Faculty of Sciences and Technology/University of AlgarveFaroPortugal
  2. 2.ISTLisboa
  3. 3.INESC-IDLisboa

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