Generative Development System for FPGA essors with Active Components
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A development environment for FPGAs has been created, which allows to build a data-flow system easily by assembling pre-designed components. To get a high-level, platform independent description we introduce Active Components. They contain several implementations for several hardware platforms and ensure correct usage of the communication interface. This offers an improved portability and reusability compared to standard FPGA modules. A comparison with a hand-crafted implementation shows its applicability without any serious drawback in resource utilization and performance.
KeywordsActive Component Processing Unit Problem Description Implementation Cost Communication Mechanism
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- 1.K. Kornmesser et al.: Simulating FPGA-Coprocessors using the FPGA Development System CHDL. Proceedings of PACT’ 98 Workshop on Reconfigurable Computing (1998).Google Scholar
- 2.P. Dillinger, S. Hezel, H. Lauer: FPGAs zur Echtzeit-Bildverarbeitung mit 1D/2D-FIR-Filteroperationen. Image Processing and Machine Vision, 213–218, VDI Berichte 1572, (2000), DüsseldorfGoogle Scholar
- 4.O. Brosch, P. Dillinger, K. Kornmesser, A. Kugel, R. Männer, M. Sessler, H. Simmler, H. Singpiel, S. Rühl, R. Lay and K.-H. Noffz, L. Levinson: MicroEnable-A Reconfigurable FPGA Coprocessor. 4th Worksh. on Electronics for LHC Experimentsi, Rome, Italy, (1998), 402–406Google Scholar
- 5.Embedded Solutions Ltd.: Handel-C Language Reference Manual (Version 2.1)Google Scholar
- 6.J. Madsen: LYCOS: The Lyngby Co-Systhesis System. Design Automation for Embedded Systems, vol. 2, nr. 2 (1997)Google Scholar
- 7.R. K. Gupta, G. De Micheli: System Synthesis Via Hardware-Software Co-Design. Computer system Labority, Stanford University (1992)Google Scholar