Generative Development System for FPGA essors with Active Components
A development environment for FPGAs has been created, which allows to build a data-flow system easily by assembling pre-designed components. To get a high-level, platform independent description we introduce Active Components. They contain several implementations for several hardware platforms and ensure correct usage of the communication interface. This offers an improved portability and reusability compared to standard FPGA modules. A comparison with a hand-crafted implementation shows its applicability without any serious drawback in resource utilization and performance.
KeywordsActive Component Processing Unit Problem Description Implementation Cost Communication Mechanism
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