Generative Development System for FPGA essors with Active Components

  • Stephan Rühl
  • Peter Dillinger
  • Stefan Hezel
  • Reinhard Männer
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

A development environment for FPGAs has been created, which allows to build a data-flow system easily by assembling pre-designed components. To get a high-level, platform independent description we introduce Active Components. They contain several implementations for several hardware platforms and ensure correct usage of the communication interface. This offers an improved portability and reusability compared to standard FPGA modules. A comparison with a hand-crafted implementation shows its applicability without any serious drawback in resource utilization and performance.

Keywords

Active Component Processing Unit Problem Description Implementation Cost Communication Mechanism 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Stephan Rühl
    • 1
  • Peter Dillinger
    • 1
  • Stefan Hezel
    • 1
  • Reinhard Männer
    • 1
  1. 1.Universität MannheimMannheimGermany

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